--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: K.39
--  \   \         Application: netgen
--  /   /         Filename: slave_interface_timesim.vhd
-- /___/   /\     Timestamp: Fri Feb 19 05:41:49 2010
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 4 -pcf slave_interface.pcf -rpw 100 -tpw 0 -ar Structure -tm slave_interface -insert_pp_buffers false -w -dir netgen/par -ofmt vhdl -sim slave_interface.ncd slave_interface_timesim.vhd 
-- Device	: 3s250epq208-4 (PRODUCTION 1.27 2008-01-09)
-- Input file	: slave_interface.ncd
-- Output file	: C:\Documents and Settings\sxs5464\Desktop\RapidFPGA\code\Xilinx Projects\Slave\netgen\par\slave_interface_timesim.vhd
-- # of Entities	: 1
-- Design Name	: slave_interface
-- Xilinx	: C:\Xilinx\10.1\ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity slave_interface is
  port (
    OEM_I2C_Clk : inout STD_LOGIC; 
    OEM_I2C_Data : inout STD_LOGIC; 
    OEM_VSYNC : out STD_LOGIC; 
    IMG0_I2C_Data : out STD_LOGIC; 
    IMG1_I2C_Clk : out STD_LOGIC; 
    IMG0_I2C_Clk : out STD_LOGIC; 
    IMG0_RST : out STD_LOGIC; 
    IMG1_ROW_EN : in STD_LOGIC := 'X'; 
    IMG1_VSYNC : in STD_LOGIC := 'X'; 
    IMG0_PIXEL_Clk : in STD_LOGIC := 'X'; 
    IMG0_VSYNC : in STD_LOGIC := 'X'; 
    OEM_ROW_EN : out STD_LOGIC; 
    IMG1_PIXEL_Clk : in STD_LOGIC := 'X'; 
    IMG1_RST : out STD_LOGIC; 
    OEM_PIXEL_Clk : out STD_LOGIC; 
    IMG0_ROW_EN : in STD_LOGIC := 'X'; 
    Clk_100MHz : in STD_LOGIC := 'X'; 
    IMG1_I2C_Data : out STD_LOGIC; 
    OEM_Data : out STD_LOGIC_VECTOR ( 9 downto 0 ); 
    LED : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    IMG0_Data : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    IMG1_Data : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    SW : in STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end slave_interface;

architecture Structure of slave_interface is
  signal Clk_100MHz_BUFGP : STD_LOGIC; 
  signal Slave_prevData_1591 : STD_LOGIC; 
  signal Slave_DataRisingEdge_1595 : STD_LOGIC; 
  signal Slave_nstate_FFd4_1597 : STD_LOGIC; 
  signal Slave_nstate_FFd1_1598 : STD_LOGIC; 
  signal Slave_N18_0 : STD_LOGIC; 
  signal N145 : STD_LOGIC; 
  signal N2_0 : STD_LOGIC; 
  signal OEM_I2C_Clk_IBUF_1604 : STD_LOGIC; 
  signal Slave_DataFallingEdge_1605 : STD_LOGIC; 
  signal Slave_nstate_FFd4_In6_0 : STD_LOGIC; 
  signal Slave_nstate_FFd3_In38_0 : STD_LOGIC; 
  signal N70_0 : STD_LOGIC; 
  signal Slave_N39 : STD_LOGIC; 
  signal Slave_N34 : STD_LOGIC; 
  signal Slave_N3 : STD_LOGIC; 
  signal Slave_N17_0 : STD_LOGIC; 
  signal Slave_delay_count_or0000_1625 : STD_LOGIC; 
  signal Slave_pstate_FFd2_1641 : STD_LOGIC; 
  signal Slave_nstate_FFd3_1642 : STD_LOGIC; 
  signal Slave_pstate_cmp_eq0002_0 : STD_LOGIC; 
  signal Slave_pstate_FFd3_1644 : STD_LOGIC; 
  signal Slave_i2cAddr_not0001_0 : STD_LOGIC; 
  signal Slave_nstate_FFd5_1646 : STD_LOGIC; 
  signal Slave_pstate_FFd2_In121_1647 : STD_LOGIC; 
  signal N98_0 : STD_LOGIC; 
  signal N68_0 : STD_LOGIC; 
  signal Slave_N391_0 : STD_LOGIC; 
  signal Slave_pstate_cmp_eq0008_0 : STD_LOGIC; 
  signal N74_0 : STD_LOGIC; 
  signal Slave_done_1655 : STD_LOGIC; 
  signal N169_0 : STD_LOGIC; 
  signal Slave_N211_0 : STD_LOGIC; 
  signal N96_0 : STD_LOGIC; 
  signal Slave_in_i2c_mux000010_0 : STD_LOGIC; 
  signal Slave_prevClk_1667 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal Slave_ClkFallingEdge_1671 : STD_LOGIC; 
  signal N76_0 : STD_LOGIC; 
  signal Slave_in_i2c_mux000022_0 : STD_LOGIC; 
  signal Slave_ack_count_cmp_eq0000_1679 : STD_LOGIC; 
  signal N8_0 : STD_LOGIC; 
  signal N14_0 : STD_LOGIC; 
  signal Slave_nstate_FFd1_In9_0 : STD_LOGIC; 
  signal Slave_ridvalid_mux00008_0 : STD_LOGIC; 
  signal Slave_nstate_FFd2_1691 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_5_Q : STD_LOGIC; 
  signal N161_0 : STD_LOGIC; 
  signal N10_0 : STD_LOGIC; 
  signal Slave_delay_count_mux0000_0_162_0 : STD_LOGIC; 
  signal Slave_shiftReg_cmp_eq000028_0 : STD_LOGIC; 
  signal Slave_ClkRisingEdge_1699 : STD_LOGIC; 
  signal N135_0 : STD_LOGIC; 
  signal Slave_pstate_FFd1_1706 : STD_LOGIC; 
  signal Slave_N31_0 : STD_LOGIC; 
  signal Slave_nstate_FFd6_1709 : STD_LOGIC; 
  signal Slave_nstate_FFd7_1710 : STD_LOGIC; 
  signal Slave_nstate_cmp_eq0000_0 : STD_LOGIC; 
  signal Slave_N28_0 : STD_LOGIC; 
  signal N28_0 : STD_LOGIC; 
  signal N130 : STD_LOGIC; 
  signal Slave_counter_mux0000_4_17_0 : STD_LOGIC; 
  signal Slave_pstate_FFd2_In65_0 : STD_LOGIC; 
  signal oem_outI2Cdata : STD_LOGIC; 
  signal Slave_nstate_FFd4_In28_0 : STD_LOGIC; 
  signal Slave_doutvalid_mux00001_0 : STD_LOGIC; 
  signal N92_0 : STD_LOGIC; 
  signal Slave_in_i2c_mux00002_0 : STD_LOGIC; 
  signal Slave_Dir_mux000080_0 : STD_LOGIC; 
  signal Slave_Dir_mux000030_0 : STD_LOGIC; 
  signal N132_0 : STD_LOGIC; 
  signal Slave_doutvalid_mux00006_0 : STD_LOGIC; 
  signal Slave_Dir_mux000069_0 : STD_LOGIC; 
  signal Slave_Dir_mux000016_0 : STD_LOGIC; 
  signal Slave_Dir_mux000064_0 : STD_LOGIC; 
  signal Slave_Dir_mux000025_0 : STD_LOGIC; 
  signal N85_0 : STD_LOGIC; 
  signal N26_0 : STD_LOGIC; 
  signal Slave_N241 : STD_LOGIC; 
  signal N52 : STD_LOGIC; 
  signal Slave_pstate_cmp_eq0010_0 : STD_LOGIC; 
  signal Slave_counter_mux0000_5_13_0 : STD_LOGIC; 
  signal N112_0 : STD_LOGIC; 
  signal Slave_N261_0 : STD_LOGIC; 
  signal N12_0 : STD_LOGIC; 
  signal N162_0 : STD_LOGIC; 
  signal N107_0 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_1 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal Slave_counter_and0000 : STD_LOGIC; 
  signal Slave_nstate_FFd3_In18_0 : STD_LOGIC; 
  signal Slave_N0 : STD_LOGIC; 
  signal Slave_N40_0 : STD_LOGIC; 
  signal N94_0 : STD_LOGIC; 
  signal Slave_delay_count_mux0000_0_124_0 : STD_LOGIC; 
  signal N133 : STD_LOGIC; 
  signal Slave_nstate_FFd4_In29_0 : STD_LOGIC; 
  signal Slave_N401_0 : STD_LOGIC; 
  signal Slave_nstate_FFd4_In40_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal Slave_Madd_delay_count_share0000_cy_1_Q : STD_LOGIC; 
  signal Slave_Madd_delay_count_share0000_cy_3_Q : STD_LOGIC; 
  signal Slave_Madd_delay_count_share0000_cy_5_Q : STD_LOGIC; 
  signal Slave_Madd_delay_count_share0000_cy_7_Q : STD_LOGIC; 
  signal Slave_Madd_delay_count_share0000_cy_9_Q : STD_LOGIC; 
  signal Slave_Madd_delay_count_share0000_cy_11_Q : STD_LOGIC; 
  signal Slave_Madd_ack_count_addsub0000_cy_1_Q : STD_LOGIC; 
  signal Slave_Madd_ack_count_addsub0000_cy_3_Q : STD_LOGIC; 
  signal Slave_Madd_ack_count_addsub0000_cy_5_Q : STD_LOGIC; 
  signal Slave_Madd_ack_count_addsub0000_cy_7_Q : STD_LOGIC; 
  signal SW_1_IBUF_1801 : STD_LOGIC; 
  signal IMG1_ROW_EN_IBUF_1802 : STD_LOGIC; 
  signal SW_2_IBUF_1803 : STD_LOGIC; 
  signal IMG1_PIXEL_Clk_IBUF_1804 : STD_LOGIC; 
  signal SW_3_IBUF_1805 : STD_LOGIC; 
  signal IMG1_Data_0_IBUF_1806 : STD_LOGIC; 
  signal IMG1_Data_1_IBUF_1807 : STD_LOGIC; 
  signal IMG1_Data_2_IBUF_1808 : STD_LOGIC; 
  signal IMG1_VSYNC_IBUF_1809 : STD_LOGIC; 
  signal IMG1_Data_3_IBUF_1810 : STD_LOGIC; 
  signal IMG1_Data_4_IBUF_1811 : STD_LOGIC; 
  signal Slave_Dir_1812 : STD_LOGIC; 
  signal IMG1_Data_5_IBUF_1813 : STD_LOGIC; 
  signal IMG1_Data_6_IBUF_1814 : STD_LOGIC; 
  signal Slave_ridvalid_1815 : STD_LOGIC; 
  signal IMG1_Data_7_IBUF_1816 : STD_LOGIC; 
  signal Slave_doutvalid_1817 : STD_LOGIC; 
  signal IMG1_Data_8_IBUF_1818 : STD_LOGIC; 
  signal IMG1_Data_9_IBUF_1819 : STD_LOGIC; 
  signal Slave_in_i2c_1820 : STD_LOGIC; 
  signal IMG0_VSYNC_IBUF_1821 : STD_LOGIC; 
  signal IMG0_Data_0_IBUF_1822 : STD_LOGIC; 
  signal IMG0_Data_1_IBUF_1823 : STD_LOGIC; 
  signal IMG0_ROW_EN_IBUF_1824 : STD_LOGIC; 
  signal IMG0_Data_2_IBUF_1825 : STD_LOGIC; 
  signal IMG0_Data_3_IBUF_1826 : STD_LOGIC; 
  signal IMG0_Data_4_IBUF_1827 : STD_LOGIC; 
  signal IMG0_Data_5_IBUF_1829 : STD_LOGIC; 
  signal IMG0_Data_6_IBUF_1830 : STD_LOGIC; 
  signal IMG0_Data_7_IBUF_1831 : STD_LOGIC; 
  signal IMG0_Data_8_IBUF_1832 : STD_LOGIC; 
  signal IMG0_Data_9_IBUF_1833 : STD_LOGIC; 
  signal IMG0_PIXEL_Clk_IBUF_1834 : STD_LOGIC; 
  signal SW_0_IBUF_1835 : STD_LOGIC; 
  signal Slave_pstate_FFd3_In28_0 : STD_LOGIC; 
  signal N111 : STD_LOGIC; 
  signal Slave_delay_count_mux0000_0_182 : STD_LOGIC; 
  signal N56 : STD_LOGIC; 
  signal Slave_nstate_FFd6_In2_SW1_O : STD_LOGIC; 
  signal Slave_shiftReg_cmp_eq0000232_O : STD_LOGIC; 
  signal Slave_delay_count_cmp_eq0000_0 : STD_LOGIC; 
  signal N86 : STD_LOGIC; 
  signal Slave_N38_0 : STD_LOGIC; 
  signal Slave_doutvalid_mux0000211_O : STD_LOGIC; 
  signal Slave_counter_mux0000_5_29_O : STD_LOGIC; 
  signal Slave_counter_0_1_1851 : STD_LOGIC; 
  signal Slave_N36_0 : STD_LOGIC; 
  signal N99_0 : STD_LOGIC; 
  signal Slave_pstate_FFd2_In192_0 : STD_LOGIC; 
  signal Slave_pstate_FFd2_In91_O : STD_LOGIC; 
  signal Slave_pstate_FFd1_In1313_1858 : STD_LOGIC; 
  signal Slave_pstate_FFd1_In26_O : STD_LOGIC; 
  signal Slave_pstate_FFd3_In50_O : STD_LOGIC; 
  signal N48 : STD_LOGIC; 
  signal Slave_Dir_and0000_0 : STD_LOGIC; 
  signal Slave_N291 : STD_LOGIC; 
  signal Slave_N32 : STD_LOGIC; 
  signal N88_0 : STD_LOGIC; 
  signal Slave_N45 : STD_LOGIC; 
  signal Slave_Dir_mux00002_0 : STD_LOGIC; 
  signal Slave_Dir_mux000039_SW0_O : STD_LOGIC; 
  signal N25_0 : STD_LOGIC; 
  signal Slave_delay_count_mux0000_0_111_0 : STD_LOGIC; 
  signal Slave_pstate_cmp_eq0009 : STD_LOGIC; 
  signal Slave_N46 : STD_LOGIC; 
  signal Slave_pstate_cmp_eq0008_SW1_O : STD_LOGIC; 
  signal Slave_nstate_FFd1_In8_O : STD_LOGIC; 
  signal Slave_pstate_FFd3_In21_SW1_O : STD_LOGIC; 
  signal Slave_nstate_FFd3_In15_O : STD_LOGIC; 
  signal N105_0 : STD_LOGIC; 
  signal Slave_nstate_FFd4_In54_SW0_O : STD_LOGIC; 
  signal Slave_nstate_cmp_eq0000_SW0_O : STD_LOGIC; 
  signal N46 : STD_LOGIC; 
  signal Slave_shiftReg_cmp_eq00001_SW1_O : STD_LOGIC; 
  signal Slave_pstate_FFd1_In1311_SW0_O : STD_LOGIC; 
  signal Slave_Dir_mux000090_O : STD_LOGIC; 
  signal Slave_counter_mux0000_5_13_SW0_O : STD_LOGIC; 
  signal Slave_counter_mux0000_4_23_O : STD_LOGIC; 
  signal Slave_in_i2c_mux000034_O : STD_LOGIC; 
  signal Slave_pstate_FFd1_In15_SW0_O : STD_LOGIC; 
  signal Slave_N311 : STD_LOGIC; 
  signal Slave_nstate_FFd3_In24_O : STD_LOGIC; 
  signal Slave_delay_count_mux0000_0_31_O : STD_LOGIC; 
  signal Slave_ack_count_mux0000_0_SW1_O : STD_LOGIC; 
  signal Slave_pstate_FFd2_In159_O : STD_LOGIC; 
  signal Slave_counter_mux0000_0_SW3_O : STD_LOGIC; 
  signal Slave_shiftReg_mux0001_7_1_SW0_O : STD_LOGIC; 
  signal Slave_ridvalid_mux000014_O : STD_LOGIC; 
  signal Slave_DataFallingEdge_not0001 : STD_LOGIC; 
  signal Slave_DataRisingEdge_DYMUX_1921 : STD_LOGIC; 
  signal Slave_DataRisingEdge_and00011 : STD_LOGIC; 
  signal Slave_DataRisingEdge_SRINV_1911 : STD_LOGIC; 
  signal Slave_DataRisingEdge_CLKINV_1910 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal Slave_shiftReg_0_DYMUX_1953 : STD_LOGIC; 
  signal Slave_shiftReg_mux0001_0_1_1950 : STD_LOGIC; 
  signal Slave_shiftReg_0_SRINV_1945 : STD_LOGIC; 
  signal Slave_shiftReg_0_CLKINV_1944 : STD_LOGIC; 
  signal Slave_nstate_FFd4_In6_1997 : STD_LOGIC; 
  signal Slave_shiftReg_1_DYMUX_1987 : STD_LOGIC; 
  signal Slave_shiftReg_mux0001_1_1_1984 : STD_LOGIC; 
  signal Slave_shiftReg_1_SRINV_1979 : STD_LOGIC; 
  signal Slave_shiftReg_1_CLKINV_1978 : STD_LOGIC; 
  signal Slave_prevData_DYMUX_2014 : STD_LOGIC; 
  signal Slave_prevData_mux0000 : STD_LOGIC; 
  signal Slave_prevData_CLKINV_2005 : STD_LOGIC; 
  signal Slave_nstate_FFd3_In38_2048 : STD_LOGIC; 
  signal Slave_shiftReg_2_DYMUX_2038 : STD_LOGIC; 
  signal Slave_shiftReg_mux0001_2_1_2035 : STD_LOGIC; 
  signal Slave_shiftReg_2_SRINV_2030 : STD_LOGIC; 
  signal Slave_shiftReg_2_CLKINV_2029 : STD_LOGIC; 
  signal N70 : STD_LOGIC; 
  signal Slave_shiftReg_3_DYMUX_2072 : STD_LOGIC; 
  signal Slave_shiftReg_mux0001_3_1_2069 : STD_LOGIC; 
  signal Slave_shiftReg_3_SRINV_2064 : STD_LOGIC; 
  signal Slave_shiftReg_3_CLKINV_2063 : STD_LOGIC; 
  signal N36 : STD_LOGIC; 
  signal Slave_shiftReg_4_DYMUX_2105 : STD_LOGIC; 
  signal Slave_shiftReg_mux0001_4_1_2102 : STD_LOGIC; 
  signal Slave_shiftReg_4_SRINV_2097 : STD_LOGIC; 
  signal Slave_shiftReg_4_CLKINV_2096 : STD_LOGIC; 
  signal N34 : STD_LOGIC; 
  signal Slave_shiftReg_5_DYMUX_2138 : STD_LOGIC; 
  signal Slave_shiftReg_mux0001_5_1_2135 : STD_LOGIC; 
  signal Slave_shiftReg_5_SRINV_2130 : STD_LOGIC; 
  signal Slave_shiftReg_5_CLKINV_2129 : STD_LOGIC; 
  signal Slave_delay_count_1_DYMUX_2164 : STD_LOGIC; 
  signal Slave_delay_count_1_CLKINV_2156 : STD_LOGIC; 
  signal Slave_delay_count_3_DXMUX_2198 : STD_LOGIC; 
  signal Slave_delay_count_3_DYMUX_2187 : STD_LOGIC; 
  signal Slave_delay_count_3_CLKINV_2179 : STD_LOGIC; 
  signal Slave_delay_count_5_DXMUX_2232 : STD_LOGIC; 
  signal Slave_delay_count_5_DYMUX_2221 : STD_LOGIC; 
  signal Slave_delay_count_5_CLKINV_2213 : STD_LOGIC; 
  signal Slave_delay_count_7_DXMUX_2266 : STD_LOGIC; 
  signal Slave_delay_count_7_DYMUX_2255 : STD_LOGIC; 
  signal Slave_delay_count_7_CLKINV_2247 : STD_LOGIC; 
  signal Slave_delay_count_9_DXMUX_2300 : STD_LOGIC; 
  signal Slave_delay_count_9_DYMUX_2289 : STD_LOGIC; 
  signal Slave_delay_count_9_CLKINV_2281 : STD_LOGIC; 
  signal Slave_i2cAddr_not0001 : STD_LOGIC; 
  signal Slave_nstate_FFd5_DYMUX_2323 : STD_LOGIC; 
  signal Slave_nstate_FFd5_In1 : STD_LOGIC; 
  signal Slave_nstate_FFd5_SRINV_2314 : STD_LOGIC; 
  signal Slave_nstate_FFd5_CLKINV_2313 : STD_LOGIC; 
  signal N98 : STD_LOGIC; 
  signal N68 : STD_LOGIC; 
  signal N74 : STD_LOGIC; 
  signal Slave_done_not0001 : STD_LOGIC; 
  signal N132 : STD_LOGIC; 
  signal Slave_doutvalid_mux00006_2909 : STD_LOGIC; 
  signal Slave_ClkEdge_1_DXMUX_2931 : STD_LOGIC; 
  signal Slave_ClkEdge_1_DYMUX_2926 : STD_LOGIC; 
  signal Slave_ClkEdge_1_CLKINV_2924 : STD_LOGIC; 
  signal Slave_Dir_mux000069_2956 : STD_LOGIC; 
  signal Slave_Dir_mux000016_2949 : STD_LOGIC; 
  signal Slave_Dir_mux000064_2980 : STD_LOGIC; 
  signal Slave_Dir_mux000025_2971 : STD_LOGIC; 
  signal N85 : STD_LOGIC; 
  signal N26 : STD_LOGIC; 
  signal Slave_counter_1_DXMUX_3035 : STD_LOGIC; 
  signal Slave_counter_mux0000_4_45 : STD_LOGIC; 
  signal Slave_pstate_cmp_eq0010_3025 : STD_LOGIC; 
  signal Slave_counter_1_SRINV_3020 : STD_LOGIC; 
  signal Slave_counter_1_CLKINV_3019 : STD_LOGIC; 
  signal Slave_counter_0_DYMUX_3047 : STD_LOGIC; 
  signal Slave_counter_0_SRINV_3045 : STD_LOGIC; 
  signal Slave_counter_0_CLKINV_3044 : STD_LOGIC; 
  signal N32 : STD_LOGIC; 
  signal N112 : STD_LOGIC; 
  signal Slave_N261 : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal N162 : STD_LOGIC; 
  signal N107 : STD_LOGIC; 
  signal Slave_nstate_FFd7_DXMUX_3150 : STD_LOGIC; 
  signal Slave_nstate_FFd7_In_3147 : STD_LOGIC; 
  signal N6_pack_1 : STD_LOGIC; 
  signal Slave_nstate_FFd7_CLKINV_3134 : STD_LOGIC; 
  signal N40 : STD_LOGIC; 
  signal Slave_nstate_FFd3_In18_3175 : STD_LOGIC; 
  signal Slave_ack_count_8_DXMUX_3204 : STD_LOGIC; 
  signal N94 : STD_LOGIC; 
  signal Slave_ack_count_8_CLKINV_3189 : STD_LOGIC; 
  signal Slave_delay_count_mux0000_0_124_3217 : STD_LOGIC; 
  signal Slave_counter_2_DXMUX_3246 : STD_LOGIC; 
  signal Slave_counter_mux0000_3_Q_3243 : STD_LOGIC; 
  signal N133_pack_1 : STD_LOGIC; 
  signal Slave_counter_2_CLKINV_3231 : STD_LOGIC; 
  signal Slave_DataFallingEdge_DYMUX_3257 : STD_LOGIC; 
  signal Slave_DataFallingEdge_SRINV_3255 : STD_LOGIC; 
  signal Slave_DataFallingEdge_CLKINV_3254 : STD_LOGIC; 
  signal Slave_nstate_FFd4_In40_3271 : STD_LOGIC; 
  signal Slave_delay_count_share0000_0_XORF_3308 : STD_LOGIC; 
  signal Slave_delay_count_share0000_0_LOGIC_ONE_3307 : STD_LOGIC; 
  signal Slave_delay_count_share0000_0_CYINIT_3306 : STD_LOGIC; 
  signal Slave_delay_count_share0000_0_CYSELF_3297 : STD_LOGIC; 
  signal Slave_delay_count_share0000_0_XORG_3293 : STD_LOGIC; 
  signal Slave_delay_count_share0000_0_CYMUXG_3292 : STD_LOGIC; 
  signal Slave_Madd_delay_count_share0000_cy_0_Q : STD_LOGIC; 
  signal Slave_delay_count_share0000_0_LOGIC_ZERO_3290 : STD_LOGIC; 
  signal Slave_delay_count_share0000_0_CYSELG_3281 : STD_LOGIC; 
  signal Slave_delay_count_share0000_0_G : STD_LOGIC; 
  signal Slave_edge_1_DXMUX_3322 : STD_LOGIC; 
  signal Slave_edge_1_DYMUX_3317 : STD_LOGIC; 
  signal Slave_edge_1_CLKINV_3315 : STD_LOGIC; 
  signal Slave_delay_count_share0000_2_XORF_3362 : STD_LOGIC; 
  signal Slave_delay_count_share0000_2_CYINIT_3361 : STD_LOGIC; 
  signal Slave_delay_count_share0000_2_F : STD_LOGIC; 
  signal Slave_delay_count_share0000_2_XORG_3350 : STD_LOGIC; 
  signal Slave_Madd_delay_count_share0000_cy_2_Q : STD_LOGIC; 
  signal Slave_delay_count_share0000_2_CYSELF_3348 : STD_LOGIC; 
  signal Slave_delay_count_share0000_2_CYMUXFAST_3347 : STD_LOGIC; 
  signal Slave_delay_count_share0000_2_CYAND_3346 : STD_LOGIC; 
  signal Slave_delay_count_share0000_2_FASTCARRY_3345 : STD_LOGIC; 
  signal Slave_delay_count_share0000_2_CYMUXG2_3344 : STD_LOGIC; 
  signal Slave_delay_count_share0000_2_CYMUXF2_3343 : STD_LOGIC; 
  signal Slave_delay_count_share0000_2_LOGIC_ZERO_3342 : STD_LOGIC; 
  signal Slave_delay_count_share0000_2_CYSELG_3333 : STD_LOGIC; 
  signal Slave_delay_count_share0000_2_G : STD_LOGIC; 
  signal N169 : STD_LOGIC; 
  signal Slave_N211 : STD_LOGIC; 
  signal N96 : STD_LOGIC; 
  signal Slave_in_i2c_mux000010_2422 : STD_LOGIC; 
  signal Slave_prevClk_DXMUX_2459 : STD_LOGIC; 
  signal Slave_prevClk_mux0000 : STD_LOGIC; 
  signal Slave_ClkFallingEdge_not0001 : STD_LOGIC; 
  signal Slave_prevClk_CLKINV_2442 : STD_LOGIC; 
  signal Slave_ClkFallingEdge_DYMUX_2470 : STD_LOGIC; 
  signal Slave_ClkFallingEdge_SRINV_2468 : STD_LOGIC; 
  signal Slave_ClkFallingEdge_CLKINV_2467 : STD_LOGIC; 
  signal N76 : STD_LOGIC; 
  signal Slave_in_i2c_mux000022_2489 : STD_LOGIC; 
  signal Slave_i2cAddr_2_DXMUX_2514 : STD_LOGIC; 
  signal Slave_i2cAddr_2_DYMUX_2508 : STD_LOGIC; 
  signal Slave_i2cAddr_2_CLKINV_2506 : STD_LOGIC; 
  signal Slave_i2cAddr_2_CEINV_2505 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal N14 : STD_LOGIC; 
  signal Slave_i2cAddr_4_DXMUX_2558 : STD_LOGIC; 
  signal Slave_i2cAddr_4_DYMUX_2552 : STD_LOGIC; 
  signal Slave_i2cAddr_4_CLKINV_2550 : STD_LOGIC; 
  signal Slave_i2cAddr_4_CEINV_2549 : STD_LOGIC; 
  signal Slave_nstate_FFd1_In9_2584 : STD_LOGIC; 
  signal Slave_ridvalid_mux00008 : STD_LOGIC; 
  signal Slave_i2cAddr_6_DXMUX_2602 : STD_LOGIC; 
  signal Slave_i2cAddr_6_DYMUX_2596 : STD_LOGIC; 
  signal Slave_i2cAddr_6_CLKINV_2594 : STD_LOGIC; 
  signal Slave_i2cAddr_6_CEINV_2593 : STD_LOGIC; 
  signal Slave_i2cAddr_7_DYMUX_2614 : STD_LOGIC; 
  signal Slave_i2cAddr_7_CLKINV_2612 : STD_LOGIC; 
  signal Slave_i2cAddr_7_CEINV_2611 : STD_LOGIC; 
  signal N161 : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal Slave_delay_count_mux0000_0_162_2664 : STD_LOGIC; 
  signal Slave_shiftReg_cmp_eq000028_2657 : STD_LOGIC; 
  signal Slave_done_DYMUX_2674 : STD_LOGIC; 
  signal Slave_done_CLKINV_2672 : STD_LOGIC; 
  signal Slave_done_CEINV_2671 : STD_LOGIC; 
  signal N135 : STD_LOGIC; 
  signal Slave_Madd_counter_addsub0000_cy_3_pack_1 : STD_LOGIC; 
  signal Slave_pstate_FFd2_In9_2724 : STD_LOGIC; 
  signal Slave_N31 : STD_LOGIC; 
  signal Slave_N28 : STD_LOGIC; 
  signal Slave_nstate_FFd1_In0_2741 : STD_LOGIC; 
  signal N28 : STD_LOGIC; 
  signal Slave_in_i2c_mux000068_2763 : STD_LOGIC; 
  signal Slave_counter_mux0000_4_17_2796 : STD_LOGIC; 
  signal Slave_pstate_FFd2_In65_2787 : STD_LOGIC; 
  signal N38 : STD_LOGIC; 
  signal N42 : STD_LOGIC; 
  signal Slave_nstate_FFd4_In28_2844 : STD_LOGIC; 
  signal Slave_doutvalid_mux00001_2836 : STD_LOGIC; 
  signal N92 : STD_LOGIC; 
  signal Slave_in_i2c_mux00002_2860 : STD_LOGIC; 
  signal Slave_Dir_mux000080_2892 : STD_LOGIC; 
  signal Slave_Dir_mux000030_2885 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_LOGIC_ZERO_3705 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_lut_2_Q_3697 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYSELF_3696 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYMUXFAST_3695 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYAND_3694 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_FASTCARRY_3693 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYMUXG2_3692 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYMUXF2_3691 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_LOGIC_ONE_3690 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYSELG_3684 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_lut_3_Q_3683 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_5_LOGIC_ONE_3736 : STD_LOGIC; 
  signal Slave_delay_count_11_rt : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYSELF_3726 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYMUXFAST_3725 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYAND_3724 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_5_FASTCARRY_3723 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYMUXG2_3722 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYMUXF2_3721 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_5_LOGIC_ZERO_3720 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYSELG_3714 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_lut_5_Q_3713 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_0_XORF_3771 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_0_LOGIC_ONE_3770 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_0_CYINIT_3769 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_0_CYSELF_3760 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_0_XORG_3756 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_0_CYMUXG_3755 : STD_LOGIC; 
  signal Slave_Madd_ack_count_addsub0000_cy_0_Q : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_0_LOGIC_ZERO_3753 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_0_CYSELG_3744 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_0_G : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_2_XORF_3809 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_2_CYINIT_3808 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_2_F : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_2_XORG_3797 : STD_LOGIC; 
  signal Slave_Madd_ack_count_addsub0000_cy_2_Q : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_2_CYSELF_3795 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_2_CYMUXFAST_3794 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_2_CYAND_3793 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_2_FASTCARRY_3792 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_2_CYMUXG2_3791 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_2_CYMUXF2_3790 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_2_LOGIC_ZERO_3789 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_2_CYSELG_3780 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_2_G : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_4_XORF_3847 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_4_CYINIT_3846 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_4_F : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_4_XORG_3835 : STD_LOGIC; 
  signal Slave_Madd_ack_count_addsub0000_cy_4_Q : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_4_CYSELF_3833 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_4_CYMUXFAST_3832 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_4_CYAND_3831 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_4_FASTCARRY_3830 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_4_CYMUXG2_3829 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_4_CYMUXF2_3828 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_4_LOGIC_ZERO_3827 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_4_CYSELG_3818 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_4_G : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_6_XORF_3885 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_6_CYINIT_3884 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_6_F : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_6_XORG_3873 : STD_LOGIC; 
  signal Slave_Madd_ack_count_addsub0000_cy_6_Q : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_6_CYSELF_3871 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_6_CYMUXFAST_3870 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_6_CYAND_3869 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_6_FASTCARRY_3868 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_6_CYMUXG2_3867 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_6_CYMUXF2_3866 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_6_LOGIC_ZERO_3865 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_6_CYSELG_3856 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_6_G : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_8_XORF_3923 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_8_CYINIT_3922 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_8_F : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_8_XORG_3911 : STD_LOGIC; 
  signal Slave_Madd_ack_count_addsub0000_cy_8_Q : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_8_CYSELF_3909 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_8_CYMUXFAST_3908 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_8_CYAND_3907 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_8_FASTCARRY_3906 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_8_CYMUXG2_3905 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_8_CYMUXF2_3904 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_8_LOGIC_ZERO_3903 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_8_CYSELG_3894 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_8_G : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_10_XORF_3954 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_10_LOGIC_ZERO_3953 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_10_CYINIT_3952 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_10_CYSELF_3943 : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_10_F : STD_LOGIC; 
  signal Slave_ack_count_addsub0000_10_XORG_3940 : STD_LOGIC; 
  signal Slave_Madd_ack_count_addsub0000_cy_10_Q : STD_LOGIC; 
  signal Slave_ack_count_11_rt_3937 : STD_LOGIC; 
  signal SW_1_INBUF : STD_LOGIC; 
  signal IMG1_ROW_EN_INBUF : STD_LOGIC; 
  signal Slave_delay_count_share0000_4_XORF_3400 : STD_LOGIC; 
  signal Slave_delay_count_share0000_4_CYINIT_3399 : STD_LOGIC; 
  signal Slave_delay_count_share0000_4_F : STD_LOGIC; 
  signal Slave_delay_count_share0000_4_XORG_3388 : STD_LOGIC; 
  signal Slave_Madd_delay_count_share0000_cy_4_Q : STD_LOGIC; 
  signal Slave_delay_count_share0000_4_CYSELF_3386 : STD_LOGIC; 
  signal Slave_delay_count_share0000_4_CYMUXFAST_3385 : STD_LOGIC; 
  signal Slave_delay_count_share0000_4_CYAND_3384 : STD_LOGIC; 
  signal Slave_delay_count_share0000_4_FASTCARRY_3383 : STD_LOGIC; 
  signal Slave_delay_count_share0000_4_CYMUXG2_3382 : STD_LOGIC; 
  signal Slave_delay_count_share0000_4_CYMUXF2_3381 : STD_LOGIC; 
  signal Slave_delay_count_share0000_4_LOGIC_ZERO_3380 : STD_LOGIC; 
  signal Slave_delay_count_share0000_4_CYSELG_3371 : STD_LOGIC; 
  signal Slave_delay_count_share0000_4_G : STD_LOGIC; 
  signal Slave_delay_count_share0000_6_XORF_3438 : STD_LOGIC; 
  signal Slave_delay_count_share0000_6_CYINIT_3437 : STD_LOGIC; 
  signal Slave_delay_count_share0000_6_F : STD_LOGIC; 
  signal Slave_delay_count_share0000_6_XORG_3426 : STD_LOGIC; 
  signal Slave_Madd_delay_count_share0000_cy_6_Q : STD_LOGIC; 
  signal Slave_delay_count_share0000_6_CYSELF_3424 : STD_LOGIC; 
  signal Slave_delay_count_share0000_6_CYMUXFAST_3423 : STD_LOGIC; 
  signal Slave_delay_count_share0000_6_CYAND_3422 : STD_LOGIC; 
  signal Slave_delay_count_share0000_6_FASTCARRY_3421 : STD_LOGIC; 
  signal Slave_delay_count_share0000_6_CYMUXG2_3420 : STD_LOGIC; 
  signal Slave_delay_count_share0000_6_CYMUXF2_3419 : STD_LOGIC; 
  signal Slave_delay_count_share0000_6_LOGIC_ZERO_3418 : STD_LOGIC; 
  signal Slave_delay_count_share0000_6_CYSELG_3409 : STD_LOGIC; 
  signal Slave_delay_count_share0000_6_G : STD_LOGIC; 
  signal Slave_delay_count_share0000_8_XORF_3476 : STD_LOGIC; 
  signal Slave_delay_count_share0000_8_CYINIT_3475 : STD_LOGIC; 
  signal Slave_delay_count_share0000_8_F : STD_LOGIC; 
  signal Slave_delay_count_share0000_8_XORG_3464 : STD_LOGIC; 
  signal Slave_Madd_delay_count_share0000_cy_8_Q : STD_LOGIC; 
  signal Slave_delay_count_share0000_8_CYSELF_3462 : STD_LOGIC; 
  signal Slave_delay_count_share0000_8_CYMUXFAST_3461 : STD_LOGIC; 
  signal Slave_delay_count_share0000_8_CYAND_3460 : STD_LOGIC; 
  signal Slave_delay_count_share0000_8_FASTCARRY_3459 : STD_LOGIC; 
  signal Slave_delay_count_share0000_8_CYMUXG2_3458 : STD_LOGIC; 
  signal Slave_delay_count_share0000_8_CYMUXF2_3457 : STD_LOGIC; 
  signal Slave_delay_count_share0000_8_LOGIC_ZERO_3456 : STD_LOGIC; 
  signal Slave_delay_count_share0000_8_CYSELG_3447 : STD_LOGIC; 
  signal Slave_delay_count_share0000_8_G : STD_LOGIC; 
  signal Slave_delay_count_share0000_10_XORF_3514 : STD_LOGIC; 
  signal Slave_delay_count_share0000_10_CYINIT_3513 : STD_LOGIC; 
  signal Slave_delay_count_share0000_10_F : STD_LOGIC; 
  signal Slave_delay_count_share0000_10_XORG_3502 : STD_LOGIC; 
  signal Slave_Madd_delay_count_share0000_cy_10_Q : STD_LOGIC; 
  signal Slave_delay_count_share0000_10_CYSELF_3500 : STD_LOGIC; 
  signal Slave_delay_count_share0000_10_CYMUXFAST_3499 : STD_LOGIC; 
  signal Slave_delay_count_share0000_10_CYAND_3498 : STD_LOGIC; 
  signal Slave_delay_count_share0000_10_FASTCARRY_3497 : STD_LOGIC; 
  signal Slave_delay_count_share0000_10_CYMUXG2_3496 : STD_LOGIC; 
  signal Slave_delay_count_share0000_10_CYMUXF2_3495 : STD_LOGIC; 
  signal Slave_delay_count_share0000_10_LOGIC_ZERO_3494 : STD_LOGIC; 
  signal Slave_delay_count_share0000_10_CYSELG_3485 : STD_LOGIC; 
  signal Slave_delay_count_share0000_10_G : STD_LOGIC; 
  signal Slave_delay_count_share0000_12_XORF_3552 : STD_LOGIC; 
  signal Slave_delay_count_share0000_12_CYINIT_3551 : STD_LOGIC; 
  signal Slave_delay_count_share0000_12_F : STD_LOGIC; 
  signal Slave_delay_count_share0000_12_XORG_3540 : STD_LOGIC; 
  signal Slave_Madd_delay_count_share0000_cy_12_Q : STD_LOGIC; 
  signal Slave_delay_count_share0000_12_CYSELF_3538 : STD_LOGIC; 
  signal Slave_delay_count_share0000_12_CYMUXFAST_3537 : STD_LOGIC; 
  signal Slave_delay_count_share0000_12_CYAND_3536 : STD_LOGIC; 
  signal Slave_delay_count_share0000_12_FASTCARRY_3535 : STD_LOGIC; 
  signal Slave_delay_count_share0000_12_CYMUXG2_3534 : STD_LOGIC; 
  signal Slave_delay_count_share0000_12_CYMUXF2_3533 : STD_LOGIC; 
  signal Slave_delay_count_share0000_12_LOGIC_ZERO_3532 : STD_LOGIC; 
  signal Slave_delay_count_share0000_12_CYSELG_3523 : STD_LOGIC; 
  signal Slave_delay_count_share0000_12_G : STD_LOGIC; 
  signal Slave_delay_count_share0000_14_XORF_3583 : STD_LOGIC; 
  signal Slave_delay_count_share0000_14_LOGIC_ZERO_3582 : STD_LOGIC; 
  signal Slave_delay_count_share0000_14_CYINIT_3581 : STD_LOGIC; 
  signal Slave_delay_count_share0000_14_CYSELF_3572 : STD_LOGIC; 
  signal Slave_delay_count_share0000_14_F : STD_LOGIC; 
  signal Slave_delay_count_share0000_14_XORG_3569 : STD_LOGIC; 
  signal Slave_Madd_delay_count_share0000_cy_14_Q : STD_LOGIC; 
  signal Slave_delay_count_15_rt_3566 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_LOGIC_ZERO_3614 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYINIT_3613 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYSELF_3604 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_lut_0_1 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYMUXG_3601 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_0_1 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_LOGIC_ONE_3599 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYSELG_3593 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_lut_1_1_3592 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_lut_2_1_3639 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYSELF_3638 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYMUXFAST_3637 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYAND_3636 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_FASTCARRY_3635 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYMUXG2_3634 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYMUXF2_3633 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3632 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYSELG_3625 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_lut_3_1_3624 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_1_LOGIC_ZERO_3674 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYINIT_3673 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYSELF_3665 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_lut_0_Q_3664 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYMUXG_3662 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_0_Q : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_1_LOGIC_ONE_3660 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYSELG_3653 : STD_LOGIC; 
  signal Slave_Mcompar_pstate_cmp_gt0000_lut_1_Q_3652 : STD_LOGIC; 
  signal IMG1_Data_6_INBUF : STD_LOGIC; 
  signal LED_2_O : STD_LOGIC; 
  signal IMG1_Data_7_INBUF : STD_LOGIC; 
  signal OEM_I2C_Clk_INBUF : STD_LOGIC; 
  signal LED_3_O : STD_LOGIC; 
  signal IMG1_Data_8_INBUF : STD_LOGIC; 
  signal IMG1_Data_9_INBUF : STD_LOGIC; 
  signal OEM_ROW_EN_O : STD_LOGIC; 
  signal OEM_VSYNC_O : STD_LOGIC; 
  signal OEM_PIXEL_Clk_O : STD_LOGIC; 
  signal IMG1_I2C_Clk_O : STD_LOGIC; 
  signal IMG1_I2C_Clk_T : STD_LOGIC; 
  signal OEM_I2C_Data_O : STD_LOGIC; 
  signal OEM_I2C_Data_T : STD_LOGIC; 
  signal OEM_I2C_Data_INBUF : STD_LOGIC; 
  signal IMG0_VSYNC_INBUF : STD_LOGIC; 
  signal IMG0_RST_O : STD_LOGIC; 
  signal IMG0_Data_0_INBUF : STD_LOGIC; 
  signal IMG0_Data_1_INBUF : STD_LOGIC; 
  signal IMG0_ROW_EN_INBUF : STD_LOGIC; 
  signal IMG0_I2C_Data_O : STD_LOGIC; 
  signal IMG0_I2C_Data_T : STD_LOGIC; 
  signal IMG0_Data_2_INBUF : STD_LOGIC; 
  signal IMG0_Data_3_INBUF : STD_LOGIC; 
  signal IMG0_Data_4_INBUF : STD_LOGIC; 
  signal Clk_100MHz_INBUF : STD_LOGIC; 
  signal SW_2_INBUF : STD_LOGIC; 
  signal IMG1_PIXEL_Clk_INBUF : STD_LOGIC; 
  signal SW_3_INBUF : STD_LOGIC; 
  signal OEM_Data_0_O : STD_LOGIC; 
  signal OEM_Data_1_O : STD_LOGIC; 
  signal OEM_Data_2_O : STD_LOGIC; 
  signal OEM_Data_3_O : STD_LOGIC; 
  signal OEM_Data_4_O : STD_LOGIC; 
  signal OEM_Data_5_O : STD_LOGIC; 
  signal OEM_Data_6_O : STD_LOGIC; 
  signal IMG1_Data_0_INBUF : STD_LOGIC; 
  signal OEM_Data_7_O : STD_LOGIC; 
  signal IMG1_Data_1_INBUF : STD_LOGIC; 
  signal OEM_Data_8_O : STD_LOGIC; 
  signal IMG1_Data_2_INBUF : STD_LOGIC; 
  signal IMG1_VSYNC_INBUF : STD_LOGIC; 
  signal OEM_Data_9_O : STD_LOGIC; 
  signal IMG1_Data_3_INBUF : STD_LOGIC; 
  signal IMG1_Data_4_INBUF : STD_LOGIC; 
  signal LED_0_O : STD_LOGIC; 
  signal IMG1_Data_5_INBUF : STD_LOGIC; 
  signal LED_1_O : STD_LOGIC; 
  signal IMG0_Data_5_INBUF : STD_LOGIC; 
  signal IMG1_RST_O : STD_LOGIC; 
  signal IMG1_I2C_Data_O : STD_LOGIC; 
  signal IMG1_I2C_Data_T : STD_LOGIC; 
  signal IMG0_Data_6_INBUF : STD_LOGIC; 
  signal IMG0_Data_7_INBUF : STD_LOGIC; 
  signal IMG0_Data_8_INBUF : STD_LOGIC; 
  signal IMG0_Data_9_INBUF : STD_LOGIC; 
  signal IMG0_PIXEL_Clk_INBUF : STD_LOGIC; 
  signal SW_0_INBUF : STD_LOGIC; 
  signal IMG0_I2C_Clk_O : STD_LOGIC; 
  signal IMG0_I2C_Clk_T : STD_LOGIC; 
  signal Clk_100MHz_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal Clk_100MHz_BUFGP_BUFG_I0_INV : STD_LOGIC; 
  signal Slave_pstate_FFd2_In26_F5MUX_4413 : STD_LOGIC; 
  signal N183 : STD_LOGIC; 
  signal Slave_pstate_FFd2_In26_BXINV_4406 : STD_LOGIC; 
  signal N182 : STD_LOGIC; 
  signal Slave_pstate_FFd3_In103_F5MUX_4438 : STD_LOGIC; 
  signal N187 : STD_LOGIC; 
  signal Slave_pstate_FFd3_In103_BXINV_4431 : STD_LOGIC; 
  signal N186 : STD_LOGIC; 
  signal N111_F5MUX_4463 : STD_LOGIC; 
  signal N164 : STD_LOGIC; 
  signal N111_BXINV_4456 : STD_LOGIC; 
  signal N163 : STD_LOGIC; 
  signal Slave_delay_count_mux0000_0_182_F5MUX_4488 : STD_LOGIC; 
  signal N185 : STD_LOGIC; 
  signal Slave_delay_count_mux0000_0_182_BXINV_4481 : STD_LOGIC; 
  signal N184 : STD_LOGIC; 
  signal Slave_counter_4_DXMUX_4517 : STD_LOGIC; 
  signal Slave_counter_4_F5MUX_4515 : STD_LOGIC; 
  signal N166 : STD_LOGIC; 
  signal Slave_counter_4_BXINV_4508 : STD_LOGIC; 
  signal N165 : STD_LOGIC; 
  signal Slave_counter_4_CLKINV_4501 : STD_LOGIC; 
  signal Slave_nstate_FFd6_DXMUX_4548 : STD_LOGIC; 
  signal Slave_nstate_FFd6_FXMUX_4547 : STD_LOGIC; 
  signal Slave_nstate_FFd6_In : STD_LOGIC; 
  signal Slave_nstate_FFd6_In2_SW1_O_pack_1 : STD_LOGIC; 
  signal Slave_nstate_FFd6_CLKINV_4533 : STD_LOGIC; 
  signal Slave_delay_count_cmp_eq0000 : STD_LOGIC; 
  signal Slave_shiftReg_cmp_eq0000232_O_pack_1 : STD_LOGIC; 
  signal Slave_N38 : STD_LOGIC; 
  signal N86_pack_1 : STD_LOGIC; 
  signal Slave_doutvalid_DXMUX_4628 : STD_LOGIC; 
  signal Slave_doutvalid_mux000057 : STD_LOGIC; 
  signal Slave_doutvalid_mux0000211_O_pack_1 : STD_LOGIC; 
  signal Slave_doutvalid_SRINV_4613 : STD_LOGIC; 
  signal Slave_doutvalid_CLKINV_4612 : STD_LOGIC; 
  signal Slave_counter_0_1_DXMUX_4662 : STD_LOGIC; 
  signal Slave_counter_0_1_FXMUX_4661 : STD_LOGIC; 
  signal Slave_counter_mux0000_5_45 : STD_LOGIC; 
  signal Slave_counter_mux0000_5_29_O_pack_1 : STD_LOGIC; 
  signal Slave_counter_0_1_SRINV_4646 : STD_LOGIC; 
  signal Slave_counter_0_1_CLKINV_4645 : STD_LOGIC; 
  signal N30 : STD_LOGIC; 
  signal Slave_N34_pack_1 : STD_LOGIC; 
  signal Slave_pstate_FFd2_DXMUX_4719 : STD_LOGIC; 
  signal Slave_pstate_FFd2_In245 : STD_LOGIC; 
  signal Slave_pstate_FFd2_In91_O_pack_1 : STD_LOGIC; 
  signal Slave_pstate_FFd2_SRINV_4704 : STD_LOGIC; 
  signal Slave_pstate_FFd2_CLKINV_4703 : STD_LOGIC; 
  signal Slave_pstate_FFd1_DXMUX_4752 : STD_LOGIC; 
  signal Slave_pstate_FFd1_In40 : STD_LOGIC; 
  signal Slave_pstate_FFd1_In26_O_pack_1 : STD_LOGIC; 
  signal Slave_pstate_FFd1_SRINV_4737 : STD_LOGIC; 
  signal Slave_pstate_FFd1_CLKINV_4736 : STD_LOGIC; 
  signal Slave_N391 : STD_LOGIC; 
  signal N56_pack_1 : STD_LOGIC; 
  signal N60 : STD_LOGIC; 
  signal Slave_pstate_FFd3_In50_O_pack_1 : STD_LOGIC; 
  signal Slave_pstate_FFd3_DXMUX_4833 : STD_LOGIC; 
  signal Slave_pstate_FFd3_In122 : STD_LOGIC; 
  signal Slave_pstate_FFd1_In1313_pack_1 : STD_LOGIC; 
  signal Slave_pstate_FFd3_SRINV_4818 : STD_LOGIC; 
  signal Slave_pstate_FFd3_CLKINV_4817 : STD_LOGIC; 
  signal Slave_N40 : STD_LOGIC; 
  signal Slave_ack_count_cmp_eq0000_pack_1 : STD_LOGIC; 
  signal N88 : STD_LOGIC; 
  signal Slave_N291_pack_1 : STD_LOGIC; 
  signal Slave_Dir_mux00002 : STD_LOGIC; 
  signal Slave_N45_pack_1 : STD_LOGIC; 
  signal Slave_Dir_mux000051_4931 : STD_LOGIC; 
  signal Slave_Dir_mux000039_SW0_O_pack_1 : STD_LOGIC; 
  signal Slave_N18 : STD_LOGIC; 
  signal Slave_N32_pack_1 : STD_LOGIC; 
  signal Slave_N17 : STD_LOGIC; 
  signal Slave_delay_count_or0000_pack_1 : STD_LOGIC; 
  signal N25 : STD_LOGIC; 
  signal Slave_N39_pack_1 : STD_LOGIC; 
  signal Slave_delay_count_0_DXMUX_5034 : STD_LOGIC; 
  signal Slave_delay_count_mux0000_0_1_5031 : STD_LOGIC; 
  signal Slave_N3_pack_1 : STD_LOGIC; 
  signal Slave_delay_count_0_SRINV_5017 : STD_LOGIC; 
  signal Slave_delay_count_0_CLKINV_5016 : STD_LOGIC; 
  signal Slave_pstate_cmp_eq0002_5060 : STD_LOGIC; 
  signal N52_pack_1 : STD_LOGIC; 
  signal Slave_nstate_FFd2_DXMUX_5089 : STD_LOGIC; 
  signal Slave_nstate_FFd2_In_5086 : STD_LOGIC; 
  signal Slave_N46_pack_1 : STD_LOGIC; 
  signal Slave_nstate_FFd2_CLKINV_5072 : STD_LOGIC; 
  signal Slave_pstate_cmp_eq0008_5114 : STD_LOGIC; 
  signal Slave_pstate_cmp_eq0008_SW1_O_pack_1 : STD_LOGIC; 
  signal Slave_nstate_FFd1_DXMUX_5145 : STD_LOGIC; 
  signal Slave_nstate_FFd1_In27 : STD_LOGIC; 
  signal Slave_nstate_FFd1_In8_O_pack_1 : STD_LOGIC; 
  signal Slave_nstate_FFd1_SRINV_5130 : STD_LOGIC; 
  signal Slave_nstate_FFd1_CLKINV_5129 : STD_LOGIC; 
  signal Slave_N401 : STD_LOGIC; 
  signal N130_pack_1 : STD_LOGIC; 
  signal Slave_pstate_FFd3_In28_5195 : STD_LOGIC; 
  signal Slave_pstate_FFd3_In21_SW1_O_pack_1 : STD_LOGIC; 
  signal Slave_ack_count_9_DXMUX_5224 : STD_LOGIC; 
  signal Slave_N0_pack_1 : STD_LOGIC; 
  signal Slave_ack_count_9_CLKINV_5209 : STD_LOGIC; 
  signal Slave_nstate_FFd3_In41_5249 : STD_LOGIC; 
  signal Slave_nstate_FFd3_In15_O_pack_1 : STD_LOGIC; 
  signal Slave_nstate_FFd4_DXMUX_5280 : STD_LOGIC; 
  signal Slave_nstate_FFd4_In79 : STD_LOGIC; 
  signal Slave_nstate_FFd4_In54_SW0_O_pack_1 : STD_LOGIC; 
  signal Slave_nstate_FFd4_SRINV_5265 : STD_LOGIC; 
  signal Slave_nstate_FFd4_CLKINV_5264 : STD_LOGIC; 
  signal Slave_nstate_cmp_eq0000_5306 : STD_LOGIC; 
  signal Slave_nstate_cmp_eq0000_SW0_O_pack_1 : STD_LOGIC; 
  signal Slave_delay_count_mux0000_0_111_5330 : STD_LOGIC; 
  signal Slave_shiftReg_cmp_eq00001_SW1_O_pack_1 : STD_LOGIC; 
  signal Slave_nstate_FFd4_In29 : STD_LOGIC; 
  signal Slave_pstate_FFd1_In1311_SW0_O_pack_1 : STD_LOGIC; 
  signal Slave_Dir_DXMUX_5385 : STD_LOGIC; 
  signal Slave_Dir_mux0000160 : STD_LOGIC; 
  signal Slave_Dir_mux000090_O_pack_1 : STD_LOGIC; 
  signal Slave_Dir_SRINV_5370 : STD_LOGIC; 
  signal Slave_Dir_CLKINV_5369 : STD_LOGIC; 
  signal Slave_counter_mux0000_5_13_5411 : STD_LOGIC; 
  signal Slave_counter_mux0000_5_13_SW0_O_pack_1 : STD_LOGIC; 
  signal Slave_counter_mux0000_4_37_5435 : STD_LOGIC; 
  signal Slave_counter_mux0000_4_23_O_pack_1 : STD_LOGIC; 
  signal Slave_in_i2c_DXMUX_5466 : STD_LOGIC; 
  signal Slave_in_i2c_mux000070 : STD_LOGIC; 
  signal Slave_in_i2c_mux000034_O_pack_1 : STD_LOGIC; 
  signal Slave_in_i2c_SRINV_5451 : STD_LOGIC; 
  signal Slave_in_i2c_CLKINV_5450 : STD_LOGIC; 
  signal Slave_N36 : STD_LOGIC; 
  signal N46_pack_1 : STD_LOGIC; 
  signal Slave_ridvalid_mux00000_5516 : STD_LOGIC; 
  signal Slave_pstate_cmp_eq0009_pack_1 : STD_LOGIC; 
  signal N99 : STD_LOGIC; 
  signal Slave_pstate_FFd2_In121_pack_1 : STD_LOGIC; 
  signal Slave_pstate_FFd1_In15_5564 : STD_LOGIC; 
  signal Slave_pstate_FFd1_In15_SW0_O_pack_1 : STD_LOGIC; 
  signal Slave_nstate_FFd3_DXMUX_5595 : STD_LOGIC; 
  signal Slave_nstate_FFd3_In55 : STD_LOGIC; 
  signal Slave_nstate_FFd3_In24_O_pack_1 : STD_LOGIC; 
  signal Slave_nstate_FFd3_SRINV_5580 : STD_LOGIC; 
  signal Slave_nstate_FFd3_CLKINV_5579 : STD_LOGIC; 
  signal N105 : STD_LOGIC; 
  signal Slave_counter_and0000_pack_1 : STD_LOGIC; 
  signal N50 : STD_LOGIC; 
  signal Slave_delay_count_mux0000_0_31_O_pack_1 : STD_LOGIC; 
  signal Slave_ack_count_0_DXMUX_5674 : STD_LOGIC; 
  signal Slave_ack_count_mux0000_0_SW1_O_pack_1 : STD_LOGIC; 
  signal Slave_ack_count_0_CLKINV_5659 : STD_LOGIC; 
  signal Slave_pstate_FFd2_In192_5699 : STD_LOGIC; 
  signal Slave_pstate_FFd2_In159_O_pack_1 : STD_LOGIC; 
  signal Slave_shiftReg_6_DXMUX_5730 : STD_LOGIC; 
  signal Slave_shiftReg_mux0001_6_1_5727 : STD_LOGIC; 
  signal N145_pack_1 : STD_LOGIC; 
  signal Slave_shiftReg_6_SRINV_5715 : STD_LOGIC; 
  signal Slave_shiftReg_6_CLKINV_5714 : STD_LOGIC; 
  signal Slave_counter_5_DXMUX_5761 : STD_LOGIC; 
  signal Slave_counter_mux0000_0_Q_5758 : STD_LOGIC; 
  signal Slave_counter_mux0000_0_SW3_O_pack_1 : STD_LOGIC; 
  signal Slave_counter_5_CLKINV_5746 : STD_LOGIC; 
  signal Slave_Dir_and0000 : STD_LOGIC; 
  signal N48_pack_1 : STD_LOGIC; 
  signal Slave_shiftReg_7_DXMUX_5815 : STD_LOGIC; 
  signal Slave_shiftReg_mux0001_7_1_SW0_O_pack_1 : STD_LOGIC; 
  signal Slave_shiftReg_7_CLKINV_5800 : STD_LOGIC; 
  signal Slave_counter_3_DXMUX_5845 : STD_LOGIC; 
  signal Slave_counter_mux0000_2_Q_5842 : STD_LOGIC; 
  signal Slave_N241_pack_1 : STD_LOGIC; 
  signal Slave_counter_3_CLKINV_5828 : STD_LOGIC; 
  signal Slave_ridvalid_DXMUX_5877 : STD_LOGIC; 
  signal Slave_ridvalid_mux000037 : STD_LOGIC; 
  signal Slave_ridvalid_mux000014_O_pack_1 : STD_LOGIC; 
  signal Slave_ridvalid_SRINV_5862 : STD_LOGIC; 
  signal Slave_ridvalid_CLKINV_5861 : STD_LOGIC; 
  signal Slave_nstate_FFd4_In19_5903 : STD_LOGIC; 
  signal Slave_N311_pack_1 : STD_LOGIC; 
  signal Slave_ClkRisingEdge_DYMUX_5922 : STD_LOGIC; 
  signal Slave_ClkRisingEdge_and00001 : STD_LOGIC; 
  signal Slave_ClkRisingEdge_SRINV_5912 : STD_LOGIC; 
  signal Slave_ClkRisingEdge_CLKINV_5911 : STD_LOGIC; 
  signal Slave_delay_count_11_DXMUX_5957 : STD_LOGIC; 
  signal Slave_delay_count_11_DYMUX_5946 : STD_LOGIC; 
  signal Slave_delay_count_11_CLKINV_5938 : STD_LOGIC; 
  signal Slave_delay_count_13_DXMUX_5991 : STD_LOGIC; 
  signal Slave_delay_count_13_DYMUX_5980 : STD_LOGIC; 
  signal Slave_delay_count_13_CLKINV_5972 : STD_LOGIC; 
  signal Slave_delay_count_15_DXMUX_6025 : STD_LOGIC; 
  signal Slave_delay_count_15_DYMUX_6014 : STD_LOGIC; 
  signal Slave_delay_count_15_CLKINV_6006 : STD_LOGIC; 
  signal Slave_ack_count_11_DXMUX_6059 : STD_LOGIC; 
  signal Slave_ack_count_11_DYMUX_6048 : STD_LOGIC; 
  signal Slave_ack_count_11_CLKINV_6040 : STD_LOGIC; 
  signal Slave_ack_count_1_DYMUX_6077 : STD_LOGIC; 
  signal Slave_ack_count_1_CLKINV_6069 : STD_LOGIC; 
  signal Slave_ack_count_3_DXMUX_6111 : STD_LOGIC; 
  signal Slave_ack_count_3_DYMUX_6100 : STD_LOGIC; 
  signal Slave_ack_count_3_CLKINV_6092 : STD_LOGIC; 
  signal Slave_ack_count_5_DXMUX_6145 : STD_LOGIC; 
  signal Slave_ack_count_5_DYMUX_6134 : STD_LOGIC; 
  signal Slave_ack_count_5_CLKINV_6126 : STD_LOGIC; 
  signal Slave_ack_count_7_DXMUX_6179 : STD_LOGIC; 
  signal Slave_ack_count_7_DYMUX_6168 : STD_LOGIC; 
  signal Slave_ack_count_7_CLKINV_6160 : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal Slave_edge : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Slave_shiftReg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Slave_delay_count : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Slave_delay_count_share0000 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Slave_counter : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal Slave_ack_count : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal Slave_ClkEdge : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Slave_i2cAddr : STD_LOGIC_VECTOR ( 7 downto 1 ); 
  signal Slave_ack_count_addsub0000 : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal Slave_Madd_counter_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal Slave_delay_count_mux0000 : STD_LOGIC_VECTOR ( 15 downto 1 ); 
  signal Slave_ack_count_mux0000 : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal Slave_Madd_delay_count_share0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Slave_Madd_ack_count_addsub0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Slave_shiftReg_mux0001 : STD_LOGIC_VECTOR ( 7 downto 7 ); 
begin
  Slave_DataRisingEdge_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X15Y45",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_DataRisingEdge_and00011,
      O => Slave_DataRisingEdge_DYMUX_1921
    );
  Slave_DataRisingEdge_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y45",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_prevData_1591,
      O => Slave_DataRisingEdge_SRINV_1911
    );
  Slave_DataRisingEdge_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y45",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_DataRisingEdge_CLKINV_1910
    );
  Slave_shiftReg_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => N2,
      O => N2_0
    );
  Slave_shiftReg_0_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg_mux0001_0_1_1950,
      O => Slave_shiftReg_0_DYMUX_1953
    );
  Slave_shiftReg_0_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => N42,
      O => Slave_shiftReg_0_SRINV_1945
    );
  Slave_shiftReg_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_shiftReg_0_CLKINV_1944
    );
  Slave_shiftReg_mux0001_0_1 : X_LUT4
    generic map(
      INIT => X"FE00",
      LOC => "SLICE_X16Y41"
    )
    port map (
      ADR0 => Slave_nstate_FFd4_1597,
      ADR1 => N145,
      ADR2 => Slave_N18_0,
      ADR3 => Slave_shiftReg(0),
      O => Slave_shiftReg_mux0001_0_1_1950
    );
  Slave_shiftReg_1_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd4_In6_1997,
      O => Slave_nstate_FFd4_In6_0
    );
  Slave_shiftReg_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg_mux0001_1_1_1984,
      O => Slave_shiftReg_1_DYMUX_1987
    );
  Slave_shiftReg_1_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => N40,
      O => Slave_shiftReg_1_SRINV_1979
    );
  Slave_shiftReg_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_shiftReg_1_CLKINV_1978
    );
  Slave_prevData_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X14Y45",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_prevData_mux0000,
      O => Slave_prevData_DYMUX_2014
    );
  Slave_prevData_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X14Y45",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_prevData_CLKINV_2005
    );
  Slave_prevData_mux00001 : X_LUT4
    generic map(
      INIT => X"FAA0",
      LOC => "SLICE_X14Y45"
    )
    port map (
      ADR0 => Slave_prevData_1591,
      ADR1 => VCC,
      ADR2 => Slave_edge(0),
      ADR3 => Slave_edge(1),
      O => Slave_prevData_mux0000
    );
  Slave_shiftReg_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd3_In38_2048,
      O => Slave_nstate_FFd3_In38_0
    );
  Slave_shiftReg_2_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X17Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg_mux0001_2_1_2035,
      O => Slave_shiftReg_2_DYMUX_2038
    );
  Slave_shiftReg_2_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X17Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => N38,
      O => Slave_shiftReg_2_SRINV_2030
    );
  Slave_shiftReg_2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X17Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_shiftReg_2_CLKINV_2029
    );
  Slave_shiftReg_3_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => N70,
      O => N70_0
    );
  Slave_shiftReg_3_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X18Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg_mux0001_3_1_2069,
      O => Slave_shiftReg_3_DYMUX_2072
    );
  Slave_shiftReg_3_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X18Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => N36,
      O => Slave_shiftReg_3_SRINV_2064
    );
  Slave_shiftReg_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X18Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_shiftReg_3_CLKINV_2063
    );
  Slave_shiftReg_4_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X19Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg_mux0001_4_1_2102,
      O => Slave_shiftReg_4_DYMUX_2105
    );
  Slave_shiftReg_4_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X19Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => N34,
      O => Slave_shiftReg_4_SRINV_2097
    );
  Slave_shiftReg_4_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X19Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_shiftReg_4_CLKINV_2096
    );
  Slave_shiftReg_5_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X19Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg_mux0001_5_1_2135,
      O => Slave_shiftReg_5_DYMUX_2138
    );
  Slave_shiftReg_5_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X19Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => N32,
      O => Slave_shiftReg_5_SRINV_2130
    );
  Slave_shiftReg_5_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X19Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_shiftReg_5_CLKINV_2129
    );
  Slave_delay_count_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(1),
      O => Slave_delay_count_1_DYMUX_2164
    );
  Slave_delay_count_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_delay_count_1_CLKINV_2156
    );
  Slave_delay_count_mux0000_1_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X20Y19"
    )
    port map (
      ADR0 => Slave_delay_count_share0000(1),
      ADR1 => Slave_delay_count(1),
      ADR2 => Slave_N3,
      ADR3 => Slave_N17_0,
      O => Slave_delay_count_mux0000(1)
    );
  Slave_delay_count_3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X22Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(3),
      O => Slave_delay_count_3_DXMUX_2198
    );
  Slave_delay_count_3_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X22Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(2),
      O => Slave_delay_count_3_DYMUX_2187
    );
  Slave_delay_count_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_delay_count_3_CLKINV_2179
    );
  Slave_delay_count_mux0000_2_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X22Y18"
    )
    port map (
      ADR0 => Slave_N3,
      ADR1 => Slave_delay_count_share0000(2),
      ADR2 => Slave_delay_count_or0000_1625,
      ADR3 => Slave_delay_count(2),
      O => Slave_delay_count_mux0000(2)
    );
  Slave_delay_count_5_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(5),
      O => Slave_delay_count_5_DXMUX_2232
    );
  Slave_delay_count_5_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(4),
      O => Slave_delay_count_5_DYMUX_2221
    );
  Slave_delay_count_5_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_delay_count_5_CLKINV_2213
    );
  Slave_delay_count_mux0000_4_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X20Y18"
    )
    port map (
      ADR0 => Slave_delay_count(4),
      ADR1 => Slave_delay_count_or0000_1625,
      ADR2 => Slave_N3,
      ADR3 => Slave_delay_count_share0000(4),
      O => Slave_delay_count_mux0000(4)
    );
  Slave_delay_count_7_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(7),
      O => Slave_delay_count_7_DXMUX_2266
    );
  Slave_delay_count_7_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(6),
      O => Slave_delay_count_7_DYMUX_2255
    );
  Slave_delay_count_7_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_delay_count_7_CLKINV_2247
    );
  Slave_delay_count_mux0000_6_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X20Y21"
    )
    port map (
      ADR0 => Slave_N3,
      ADR1 => Slave_N17_0,
      ADR2 => Slave_delay_count_share0000(6),
      ADR3 => Slave_delay_count(6),
      O => Slave_delay_count_mux0000(6)
    );
  Slave_delay_count_9_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X23Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(9),
      O => Slave_delay_count_9_DXMUX_2300
    );
  Slave_delay_count_9_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X23Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(8),
      O => Slave_delay_count_9_DYMUX_2289
    );
  Slave_delay_count_9_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X23Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_delay_count_9_CLKINV_2281
    );
  Slave_delay_count_mux0000_8_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X23Y20"
    )
    port map (
      ADR0 => Slave_N3,
      ADR1 => Slave_delay_count_or0000_1625,
      ADR2 => Slave_delay_count_share0000(8),
      ADR3 => Slave_delay_count(8),
      O => Slave_delay_count_mux0000(8)
    );
  Slave_nstate_FFd5_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_i2cAddr_not0001,
      O => Slave_i2cAddr_not0001_0
    );
  Slave_nstate_FFd5_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd5_In1,
      O => Slave_nstate_FFd5_DYMUX_2323
    );
  Slave_nstate_FFd5_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd2_1641,
      O => Slave_nstate_FFd5_SRINV_2314
    );
  Slave_nstate_FFd5_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_nstate_FFd5_CLKINV_2313
    );
  N98_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => N98,
      O => N98_0
    );
  N98_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => N68,
      O => N68_0
    );
  Slave_nstate_FFd3_In24_SW0 : X_LUT4
    generic map(
      INIT => X"FFCC",
      LOC => "SLICE_X14Y41"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_pstate_FFd3_1644,
      ADR2 => VCC,
      ADR3 => Slave_pstate_FFd2_1641,
      O => N68
    );
  N74_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => N74,
      O => N74_0
    );
  N132_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => N132,
      O => N132_0
    );
  N132_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_doutvalid_mux00006_2909,
      O => Slave_doutvalid_mux00006_0
    );
  Slave_doutvalid_mux00006 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X16Y29"
    )
    port map (
      ADR0 => Slave_nstate_FFd5_1646,
      ADR1 => Slave_nstate_FFd6_1709,
      ADR2 => Slave_nstate_FFd3_1642,
      ADR3 => Slave_nstate_FFd1_1598,
      O => Slave_doutvalid_mux00006_2909
    );
  Slave_ClkEdge_1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X19Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ClkEdge(0),
      O => Slave_ClkEdge_1_DXMUX_2931
    );
  Slave_ClkEdge_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X19Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => OEM_I2C_Clk_IBUF_1604,
      O => Slave_ClkEdge_1_DYMUX_2926
    );
  Slave_ClkEdge_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X19Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_ClkEdge_1_CLKINV_2924
    );
  Slave_Dir_mux000069_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Dir_mux000069_2956,
      O => Slave_Dir_mux000069_0
    );
  Slave_Dir_mux000069_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Dir_mux000016_2949,
      O => Slave_Dir_mux000016_0
    );
  Slave_Dir_mux000016 : X_LUT4
    generic map(
      INIT => X"0400",
      LOC => "SLICE_X21Y27"
    )
    port map (
      ADR0 => Slave_delay_count(0),
      ADR1 => Slave_delay_count(11),
      ADR2 => Slave_delay_count(5),
      ADR3 => Slave_delay_count(4),
      O => Slave_Dir_mux000016_2949
    );
  Slave_Dir_mux000064_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Dir_mux000064_2980,
      O => Slave_Dir_mux000064_0
    );
  Slave_Dir_mux000064_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Dir_mux000025_2971,
      O => Slave_Dir_mux000025_0
    );
  Slave_Dir_mux000025 : X_LUT4
    generic map(
      INIT => X"8080",
      LOC => "SLICE_X21Y26"
    )
    port map (
      ADR0 => Slave_delay_count(9),
      ADR1 => Slave_delay_count(10),
      ADR2 => Slave_nstate_FFd2_1691,
      ADR3 => VCC,
      O => Slave_Dir_mux000025_2971
    );
  N85_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => N85,
      O => N85_0
    );
  N85_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => N26,
      O => N26_0
    );
  Slave_counter_mux0000_2_SW1 : X_LUT4
    generic map(
      INIT => X"2AAA",
      LOC => "SLICE_X14Y33"
    )
    port map (
      ADR0 => Slave_nstate_FFd3_1642,
      ADR1 => Slave_counter(1),
      ADR2 => Slave_counter(2),
      ADR3 => Slave_counter(0),
      O => N26
    );
  Slave_counter_1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_mux0000_4_45,
      O => Slave_counter_1_DXMUX_3035
    );
  Slave_counter_1_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_cmp_eq0010_3025,
      O => Slave_pstate_cmp_eq0010_0
    );
  Slave_counter_1_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_mux0000_4_37_5435,
      O => Slave_counter_1_SRINV_3020
    );
  Slave_counter_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_counter_1_CLKINV_3019
    );
  Slave_counter_0_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X17Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_0_1_FXMUX_4661,
      O => Slave_counter_0_DYMUX_3047
    );
  Slave_counter_0_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X17Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_mux0000_5_13_0,
      O => Slave_counter_0_SRINV_3045
    );
  Slave_counter_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X17Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_counter_0_CLKINV_3044
    );
  N32_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => N112,
      O => N112_0
    );
  Slave_shiftReg_mux0001_0_122_SW2 : X_LUT4
    generic map(
      INIT => X"EAAA",
      LOC => "SLICE_X19Y38"
    )
    port map (
      ADR0 => Slave_shiftReg(7),
      ADR1 => Slave_nstate_FFd3_1642,
      ADR2 => Slave_shiftReg(6),
      ADR3 => Slave_ClkRisingEdge_1699,
      O => N112
    );
  Slave_N261_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N261,
      O => Slave_N261_0
    );
  Slave_N261_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => N12,
      O => N12_0
    );
  Slave_ack_count_cmp_eq0000_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X22Y32"
    )
    port map (
      ADR0 => Slave_ack_count(0),
      ADR1 => Slave_ack_count(1),
      ADR2 => Slave_ack_count(5),
      ADR3 => Slave_ack_count(2),
      O => N12
    );
  N162_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => N162,
      O => N162_0
    );
  N162_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => N107,
      O => N107_0
    );
  Slave_pstate_FFd3_In21_SW0 : X_LUT4
    generic map(
      INIT => X"D5C0",
      LOC => "SLICE_X15Y40"
    )
    port map (
      ADR0 => Slave_pstate_FFd2_1641,
      ADR1 => Slave_DataRisingEdge_1595,
      ADR2 => OEM_I2C_Clk_IBUF_1604,
      ADR3 => Slave_pstate_FFd1_1706,
      O => N107
    );
  Slave_nstate_FFd7_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X19Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd7_In_3147,
      O => Slave_nstate_FFd7_DXMUX_3150
    );
  Slave_nstate_FFd7_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => N6_pack_1,
      O => N6
    );
  Slave_nstate_FFd7_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X19Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_nstate_FFd7_CLKINV_3134
    );
  Slave_nstate_FFd7_In_SW0 : X_LUT4
    generic map(
      INIT => X"88FF",
      LOC => "SLICE_X19Y33"
    )
    port map (
      ADR0 => Slave_DataRisingEdge_1595,
      ADR1 => OEM_I2C_Clk_IBUF_1604,
      ADR2 => VCC,
      ADR3 => Slave_nstate_FFd7_1710,
      O => N6_pack_1
    );
  Slave_shiftReg_mux0001_1_SW0 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y42"
    )
    port map (
      ADR0 => Slave_shiftReg(0),
      ADR1 => Slave_N39,
      ADR2 => Slave_shiftReg(2),
      ADR3 => Slave_N34,
      O => N40
    );
  Slave_nstate_FFd3_In18_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd3_In18_3175,
      O => Slave_nstate_FFd3_In18_0
    );
  Slave_nstate_FFd3_In18 : X_LUT4
    generic map(
      INIT => X"2000",
      LOC => "SLICE_X17Y34"
    )
    port map (
      ADR0 => Slave_counter_and0000,
      ADR1 => Slave_counter(3),
      ADR2 => Slave_i2cAddr(7),
      ADR3 => Slave_counter(0),
      O => Slave_nstate_FFd3_In18_3175
    );
  Slave_ack_count_8_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X22Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_mux0000(8),
      O => Slave_ack_count_8_DXMUX_3204
    );
  Slave_ack_count_8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => N94,
      O => N94_0
    );
  Slave_ack_count_8_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_ack_count_8_CLKINV_3189
    );
  Slave_ack_count_cmp_eq00001_SW2 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X22Y35"
    )
    port map (
      ADR0 => Slave_ack_count(8),
      ADR1 => Slave_ack_count(7),
      ADR2 => Slave_ack_count(4),
      ADR3 => Slave_ack_count(6),
      O => N94
    );
  Slave_delay_count_mux0000_0_124_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000_0_124_3217,
      O => Slave_delay_count_mux0000_0_124_0
    );
  Slave_delay_count_mux0000_0_124 : X_LUT4
    generic map(
      INIT => X"7FFF",
      LOC => "SLICE_X18Y20"
    )
    port map (
      ADR0 => Slave_delay_count(10),
      ADR1 => Slave_delay_count(3),
      ADR2 => Slave_delay_count(7),
      ADR3 => Slave_delay_count(4),
      O => Slave_delay_count_mux0000_0_124_3217
    );
  Slave_counter_2_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X17Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_mux0000_3_Q_3243,
      O => Slave_counter_2_DXMUX_3246
    );
  Slave_counter_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => N133_pack_1,
      O => N133
    );
  Slave_counter_2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X17Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_counter_2_CLKINV_3231
    );
  Slave_counter_mux0000_3_SW3 : X_LUT4
    generic map(
      INIT => X"AEEE",
      LOC => "SLICE_X17Y29"
    )
    port map (
      ADR0 => Slave_nstate_FFd2_1691,
      ADR1 => Slave_nstate_FFd3_1642,
      ADR2 => Slave_counter(1),
      ADR3 => Slave_counter(0),
      O => N133_pack_1
    );
  Slave_DataFallingEdge_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X15Y43",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => Slave_DataFallingEdge_DYMUX_3257
    );
  Slave_DataFallingEdge_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y43",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_DataFallingEdge_not0001,
      O => Slave_DataFallingEdge_SRINV_3255
    );
  Slave_DataFallingEdge_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y43",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_DataFallingEdge_CLKINV_3254
    );
  Slave_nstate_FFd4_In40_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd4_In40_3271,
      O => Slave_nstate_FFd4_In40_0
    );
  Slave_nstate_FFd4_In40 : X_LUT4
    generic map(
      INIT => X"8A0A",
      LOC => "SLICE_X16Y36"
    )
    port map (
      ADR0 => Slave_nstate_FFd1_1598,
      ADR1 => Slave_nstate_FFd4_In29_0,
      ADR2 => Slave_pstate_cmp_eq0008_0,
      ADR3 => Slave_N401_0,
      O => Slave_nstate_FFd4_In40_3271
    );
  Slave_delay_count_share0000_0_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y17"
    )
    port map (
      O => Slave_delay_count_share0000_0_LOGIC_ZERO_3290
    );
  Slave_delay_count_share0000_0_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X21Y17"
    )
    port map (
      O => Slave_delay_count_share0000_0_LOGIC_ONE_3307
    );
  Slave_delay_count_share0000_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_0_XORF_3308,
      O => Slave_delay_count_share0000(0)
    );
  Slave_delay_count_share0000_0_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y17"
    )
    port map (
      I0 => Slave_delay_count_share0000_0_CYINIT_3306,
      I1 => Slave_Madd_delay_count_share0000_lut(0),
      O => Slave_delay_count_share0000_0_XORF_3308
    );
  Slave_delay_count_share0000_0_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y17"
    )
    port map (
      IA => Slave_delay_count_share0000_0_LOGIC_ONE_3307,
      IB => Slave_delay_count_share0000_0_CYINIT_3306,
      SEL => Slave_delay_count_share0000_0_CYSELF_3297,
      O => Slave_Madd_delay_count_share0000_cy_0_Q
    );
  Slave_delay_count_share0000_0_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => Slave_delay_count_share0000_0_CYINIT_3306
    );
  Slave_delay_count_share0000_0_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_delay_count_share0000_lut(0),
      O => Slave_delay_count_share0000_0_CYSELF_3297
    );
  Slave_delay_count_share0000_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_0_XORG_3293,
      O => Slave_delay_count_share0000(1)
    );
  Slave_delay_count_share0000_0_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y17"
    )
    port map (
      I0 => Slave_Madd_delay_count_share0000_cy_0_Q,
      I1 => Slave_delay_count_share0000_0_G,
      O => Slave_delay_count_share0000_0_XORG_3293
    );
  Slave_delay_count_share0000_0_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_0_CYMUXG_3292,
      O => Slave_Madd_delay_count_share0000_cy_1_Q
    );
  Slave_delay_count_share0000_0_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X21Y17"
    )
    port map (
      IA => Slave_delay_count_share0000_0_LOGIC_ZERO_3290,
      IB => Slave_Madd_delay_count_share0000_cy_0_Q,
      SEL => Slave_delay_count_share0000_0_CYSELG_3281,
      O => Slave_delay_count_share0000_0_CYMUXG_3292
    );
  Slave_delay_count_share0000_0_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_0_G,
      O => Slave_delay_count_share0000_0_CYSELG_3281
    );
  Slave_edge_1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X15Y44",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_edge(0),
      O => Slave_edge_1_DXMUX_3322
    );
  Slave_edge_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X15Y44",
      PATHPULSE => 798 ps
    )
    port map (
      I => oem_outI2Cdata,
      O => Slave_edge_1_DYMUX_3317
    );
  Slave_edge_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y44",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_edge_1_CLKINV_3315
    );
  Slave_delay_count_share0000_2_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y18"
    )
    port map (
      O => Slave_delay_count_share0000_2_LOGIC_ZERO_3342
    );
  Slave_delay_count_share0000_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_2_XORF_3362,
      O => Slave_delay_count_share0000(2)
    );
  Slave_delay_count_share0000_2_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y18"
    )
    port map (
      I0 => Slave_delay_count_share0000_2_CYINIT_3361,
      I1 => Slave_delay_count_share0000_2_F,
      O => Slave_delay_count_share0000_2_XORF_3362
    );
  Slave_delay_count_share0000_2_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y18"
    )
    port map (
      IA => Slave_delay_count_share0000_2_LOGIC_ZERO_3342,
      IB => Slave_delay_count_share0000_2_CYINIT_3361,
      SEL => Slave_delay_count_share0000_2_CYSELF_3348,
      O => Slave_Madd_delay_count_share0000_cy_2_Q
    );
  Slave_delay_count_share0000_2_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y18"
    )
    port map (
      IA => Slave_delay_count_share0000_2_LOGIC_ZERO_3342,
      IB => Slave_delay_count_share0000_2_LOGIC_ZERO_3342,
      SEL => Slave_delay_count_share0000_2_CYSELF_3348,
      O => Slave_delay_count_share0000_2_CYMUXF2_3343
    );
  Slave_delay_count_share0000_2_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_delay_count_share0000_cy_1_Q,
      O => Slave_delay_count_share0000_2_CYINIT_3361
    );
  Slave_delay_count_share0000_2_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_2_F,
      O => Slave_delay_count_share0000_2_CYSELF_3348
    );
  Slave_delay_count_share0000_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_2_XORG_3350,
      O => Slave_delay_count_share0000(3)
    );
  Slave_delay_count_share0000_2_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y18"
    )
    port map (
      I0 => Slave_Madd_delay_count_share0000_cy_2_Q,
      I1 => Slave_delay_count_share0000_2_G,
      O => Slave_delay_count_share0000_2_XORG_3350
    );
  Slave_delay_count_share0000_2_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_2_CYMUXFAST_3347,
      O => Slave_Madd_delay_count_share0000_cy_3_Q
    );
  Slave_delay_count_share0000_2_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_delay_count_share0000_cy_1_Q,
      O => Slave_delay_count_share0000_2_FASTCARRY_3345
    );
  Slave_delay_count_share0000_2_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y18"
    )
    port map (
      I0 => Slave_delay_count_share0000_2_CYSELG_3333,
      I1 => Slave_delay_count_share0000_2_CYSELF_3348,
      O => Slave_delay_count_share0000_2_CYAND_3346
    );
  Slave_delay_count_share0000_2_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y18"
    )
    port map (
      IA => Slave_delay_count_share0000_2_CYMUXG2_3344,
      IB => Slave_delay_count_share0000_2_FASTCARRY_3345,
      SEL => Slave_delay_count_share0000_2_CYAND_3346,
      O => Slave_delay_count_share0000_2_CYMUXFAST_3347
    );
  Slave_delay_count_share0000_2_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y18"
    )
    port map (
      IA => Slave_delay_count_share0000_2_LOGIC_ZERO_3342,
      IB => Slave_delay_count_share0000_2_CYMUXF2_3343,
      SEL => Slave_delay_count_share0000_2_CYSELG_3333,
      O => Slave_delay_count_share0000_2_CYMUXG2_3344
    );
  Slave_delay_count_share0000_2_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_2_G,
      O => Slave_delay_count_share0000_2_CYSELG_3333
    );
  Slave_done_not00011 : X_LUT4
    generic map(
      INIT => X"4000",
      LOC => "SLICE_X15Y31"
    )
    port map (
      ADR0 => Slave_counter(2),
      ADR1 => Slave_pstate_cmp_eq0008_0,
      ADR2 => Slave_nstate_FFd1_1598,
      ADR3 => Slave_N391_0,
      O => Slave_done_not0001
    );
  N169_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => N169,
      O => N169_0
    );
  N169_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N211,
      O => Slave_N211_0
    );
  Slave_doutvalid_mux000021 : X_LUT4
    generic map(
      INIT => X"5D5F",
      LOC => "SLICE_X16Y30"
    )
    port map (
      ADR0 => OEM_I2C_Clk_IBUF_1604,
      ADR1 => Slave_done_1655,
      ADR2 => Slave_DataFallingEdge_1605,
      ADR3 => Slave_DataRisingEdge_1595,
      O => Slave_N211
    );
  N96_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => N96,
      O => N96_0
    );
  N96_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_in_i2c_mux000010_2422,
      O => Slave_in_i2c_mux000010_0
    );
  Slave_in_i2c_mux000010 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X23Y34"
    )
    port map (
      ADR0 => Slave_ack_count(11),
      ADR1 => Slave_ack_count(10),
      ADR2 => Slave_ack_count(3),
      ADR3 => Slave_ack_count(2),
      O => Slave_in_i2c_mux000010_2422
    );
  Slave_prevClk_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X19Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_prevClk_mux0000,
      O => Slave_prevClk_DXMUX_2459
    );
  Slave_prevClk_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X19Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_prevClk_CLKINV_2442
    );
  Slave_ClkFallingEdge_not00011 : X_LUT4
    generic map(
      INIT => X"EFEF",
      LOC => "SLICE_X19Y36"
    )
    port map (
      ADR0 => Slave_ClkEdge(1),
      ADR1 => Slave_ClkEdge(0),
      ADR2 => Slave_prevClk_1667,
      ADR3 => VCC,
      O => Slave_ClkFallingEdge_not0001
    );
  Slave_ClkFallingEdge_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X21Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => Slave_ClkFallingEdge_DYMUX_2470
    );
  Slave_ClkFallingEdge_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X21Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ClkFallingEdge_not0001,
      O => Slave_ClkFallingEdge_SRINV_2468
    );
  Slave_ClkFallingEdge_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X21Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_ClkFallingEdge_CLKINV_2467
    );
  N76_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => N76,
      O => N76_0
    );
  N76_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_in_i2c_mux000022_2489,
      O => Slave_in_i2c_mux000022_0
    );
  Slave_in_i2c_mux000022 : X_LUT4
    generic map(
      INIT => X"FFEF",
      LOC => "SLICE_X23Y35"
    )
    port map (
      ADR0 => Slave_ack_count(7),
      ADR1 => Slave_ack_count(4),
      ADR2 => Slave_ack_count(1),
      ADR3 => Slave_ack_count(9),
      O => Slave_in_i2c_mux000022_2489
    );
  Slave_i2cAddr_2_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X18Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg(2),
      O => Slave_i2cAddr_2_DXMUX_2514
    );
  Slave_i2cAddr_2_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X18Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg(1),
      O => Slave_i2cAddr_2_DYMUX_2508
    );
  Slave_i2cAddr_2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X18Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_i2cAddr_2_CLKINV_2506
    );
  Slave_i2cAddr_2_CEINV : X_BUF
    generic map(
      LOC => "SLICE_X18Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_i2cAddr_not0001_0,
      O => Slave_i2cAddr_2_CEINV_2505
    );
  N8_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => N8,
      O => N8_0
    );
  N8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => N14,
      O => N14_0
    );
  Slave_ack_count_mux0000_0_SW0 : X_LUT4
    generic map(
      INIT => X"E040",
      LOC => "SLICE_X23Y30"
    )
    port map (
      ADR0 => Slave_ack_count_cmp_eq0000_1679,
      ADR1 => Slave_ack_count_addsub0000(0),
      ADR2 => Slave_nstate_FFd1_1598,
      ADR3 => Slave_ClkFallingEdge_1671,
      O => N14
    );
  Slave_i2cAddr_4_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X19Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg(4),
      O => Slave_i2cAddr_4_DXMUX_2558
    );
  Slave_i2cAddr_4_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X19Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg(3),
      O => Slave_i2cAddr_4_DYMUX_2552
    );
  Slave_i2cAddr_4_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X19Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_i2cAddr_4_CLKINV_2550
    );
  Slave_i2cAddr_4_CEINV : X_BUF
    generic map(
      LOC => "SLICE_X19Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_i2cAddr_not0001_0,
      O => Slave_i2cAddr_4_CEINV_2549
    );
  Slave_nstate_FFd1_In9_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X12Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd1_In9_2584,
      O => Slave_nstate_FFd1_In9_0
    );
  Slave_nstate_FFd1_In9_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X12Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ridvalid_mux00008,
      O => Slave_ridvalid_mux00008_0
    );
  Slave_pstate_FFd2_In11 : X_LUT4
    generic map(
      INIT => X"3F3F",
      LOC => "SLICE_X12Y39"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_DataRisingEdge_1595,
      ADR2 => OEM_I2C_Clk_IBUF_1604,
      ADR3 => VCC,
      O => Slave_ridvalid_mux00008
    );
  Slave_i2cAddr_6_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X18Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg(6),
      O => Slave_i2cAddr_6_DXMUX_2602
    );
  Slave_i2cAddr_6_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X18Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg(5),
      O => Slave_i2cAddr_6_DYMUX_2596
    );
  Slave_i2cAddr_6_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X18Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_i2cAddr_6_CLKINV_2594
    );
  Slave_i2cAddr_6_CEINV : X_BUF
    generic map(
      LOC => "SLICE_X18Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_i2cAddr_not0001_0,
      O => Slave_i2cAddr_6_CEINV_2593
    );
  Slave_i2cAddr_7_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X19Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg(7),
      O => Slave_i2cAddr_7_DYMUX_2614
    );
  Slave_i2cAddr_7_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X19Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_i2cAddr_7_CLKINV_2612
    );
  Slave_i2cAddr_7_CEINV : X_BUF
    generic map(
      LOC => "SLICE_X19Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_i2cAddr_not0001_0,
      O => Slave_i2cAddr_7_CEINV_2611
    );
  N161_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => N161,
      O => N161_0
    );
  N161_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => N10,
      O => N10_0
    );
  Slave_nstate_FFd2_In_SW0 : X_LUT4
    generic map(
      INIT => X"F777",
      LOC => "SLICE_X17Y37"
    )
    port map (
      ADR0 => Slave_Mcompar_pstate_cmp_gt0000_cy_5_Q,
      ADR1 => Slave_nstate_FFd2_1691,
      ADR2 => Slave_DataRisingEdge_1595,
      ADR3 => OEM_I2C_Clk_IBUF_1604,
      O => N10
    );
  Slave_delay_count_mux0000_0_162_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000_0_162_2664,
      O => Slave_delay_count_mux0000_0_162_0
    );
  Slave_delay_count_mux0000_0_162_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg_cmp_eq000028_2657,
      O => Slave_shiftReg_cmp_eq000028_0
    );
  Slave_shiftReg_cmp_eq000028 : X_LUT4
    generic map(
      INIT => X"0005",
      LOC => "SLICE_X22Y20"
    )
    port map (
      ADR0 => Slave_delay_count(8),
      ADR1 => VCC,
      ADR2 => Slave_delay_count(0),
      ADR3 => Slave_delay_count(10),
      O => Slave_shiftReg_cmp_eq000028_2657
    );
  Slave_done_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X15Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => Slave_done_DYMUX_2674
    );
  Slave_done_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_done_CLKINV_2672
    );
  Slave_done_CEINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_done_not0001,
      O => Slave_done_CEINV_2671
    );
  N135_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => N135,
      O => N135_0
    );
  N135_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_counter_addsub0000_cy_3_pack_1,
      O => Slave_Madd_counter_addsub0000_cy(3)
    );
  Slave_Madd_counter_addsub0000_cy_3_11 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X15Y29"
    )
    port map (
      ADR0 => Slave_counter(2),
      ADR1 => Slave_counter(0),
      ADR2 => Slave_counter(3),
      ADR3 => Slave_counter(1),
      O => Slave_Madd_counter_addsub0000_cy_3_pack_1
    );
  Slave_pstate_FFd2_In9_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N31,
      O => Slave_N31_0
    );
  Slave_pstate_FFd2_In41 : X_LUT4
    generic map(
      INIT => X"3737",
      LOC => "SLICE_X14Y40"
    )
    port map (
      ADR0 => Slave_DataRisingEdge_1595,
      ADR1 => OEM_I2C_Clk_IBUF_1604,
      ADR2 => Slave_DataFallingEdge_1605,
      ADR3 => VCC,
      O => Slave_N31
    );
  Slave_N28_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N28,
      O => Slave_N28_0
    );
  Slave_nstate_FFd1_In0 : X_LUT4
    generic map(
      INIT => X"F000",
      LOC => "SLICE_X17Y36"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Slave_nstate_FFd5_1646,
      ADR3 => Slave_nstate_cmp_eq0000_0,
      O => Slave_nstate_FFd1_In0_2741
    );
  N28_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => N28,
      O => N28_0
    );
  Slave_in_i2c_mux000068 : X_LUT4
    generic map(
      INIT => X"C000",
      LOC => "SLICE_X21Y38"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_nstate_FFd2_1691,
      ADR2 => Slave_ClkFallingEdge_1671,
      ADR3 => Slave_shiftReg(0),
      O => Slave_in_i2c_mux000068_2763
    );
  Slave_counter_mux0000_4_17_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X13Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_mux0000_4_17_2796,
      O => Slave_counter_mux0000_4_17_0
    );
  Slave_counter_mux0000_4_17_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X13Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd2_In65_2787,
      O => Slave_pstate_FFd2_In65_0
    );
  Slave_pstate_FFd2_In65 : X_LUT4
    generic map(
      INIT => X"1111",
      LOC => "SLICE_X13Y35"
    )
    port map (
      ADR0 => Slave_counter(5),
      ADR1 => N130,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_pstate_FFd2_In65_2787
    );
  Slave_shiftReg_mux0001_0_SW0 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X17Y40"
    )
    port map (
      ADR0 => Slave_N34,
      ADR1 => Slave_N39,
      ADR2 => Slave_shiftReg(1),
      ADR3 => oem_outI2Cdata,
      O => N42
    );
  Slave_nstate_FFd4_In28_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd4_In28_2844,
      O => Slave_nstate_FFd4_In28_0
    );
  Slave_nstate_FFd4_In28_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_doutvalid_mux00001_2836,
      O => Slave_doutvalid_mux00001_0
    );
  Slave_doutvalid_mux00001 : X_LUT4
    generic map(
      INIT => X"EEEE",
      LOC => "SLICE_X17Y39"
    )
    port map (
      ADR0 => Slave_nstate_FFd7_1710,
      ADR1 => Slave_nstate_FFd2_1691,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_doutvalid_mux00001_2836
    );
  N92_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => N92,
      O => N92_0
    );
  N92_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_in_i2c_mux00002_2860,
      O => Slave_in_i2c_mux00002_0
    );
  Slave_in_i2c_mux00002 : X_LUT4
    generic map(
      INIT => X"2222",
      LOC => "SLICE_X21Y35"
    )
    port map (
      ADR0 => Slave_nstate_FFd2_1691,
      ADR1 => Slave_ClkFallingEdge_1671,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_in_i2c_mux00002_2860
    );
  Slave_Dir_mux000030 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X22Y26"
    )
    port map (
      ADR0 => Slave_delay_count(7),
      ADR1 => Slave_delay_count(2),
      ADR2 => Slave_delay_count(3),
      ADR3 => Slave_delay_count(8),
      O => Slave_Dir_mux000030_2885
    );
  Slave_Dir_mux000080_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Dir_mux000080_2892,
      O => Slave_Dir_mux000080_0
    );
  Slave_Dir_mux000080_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Dir_mux000030_2885,
      O => Slave_Dir_mux000030_0
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X19Y24"
    )
    port map (
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_LOGIC_ONE_3690
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X19Y24"
    )
    port map (
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_LOGIC_ZERO_3705
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X19Y24"
    )
    port map (
      IA => Slave_Mcompar_pstate_cmp_gt0000_cy_3_LOGIC_ZERO_3705,
      IB => Slave_Mcompar_pstate_cmp_gt0000_cy_3_LOGIC_ZERO_3705,
      SEL => Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYSELF_3696,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYMUXF2_3691
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X19Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Mcompar_pstate_cmp_gt0000_lut_2_Q_3697,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYSELF_3696
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X19Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYMUXG_3662,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_FASTCARRY_3693
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X19Y24"
    )
    port map (
      I0 => Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYSELG_3684,
      I1 => Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYSELF_3696,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYAND_3694
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X19Y24"
    )
    port map (
      IA => Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYMUXG2_3692,
      IB => Slave_Mcompar_pstate_cmp_gt0000_cy_3_FASTCARRY_3693,
      SEL => Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYAND_3694,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYMUXFAST_3695
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X19Y24"
    )
    port map (
      IA => Slave_Mcompar_pstate_cmp_gt0000_cy_3_LOGIC_ONE_3690,
      IB => Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYMUXF2_3691,
      SEL => Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYSELG_3684,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYMUXG2_3692
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X19Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Mcompar_pstate_cmp_gt0000_lut_3_Q_3683,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYSELG_3684
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_5_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X19Y25"
    )
    port map (
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_5_LOGIC_ZERO_3720
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_5_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X19Y25"
    )
    port map (
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_5_LOGIC_ONE_3736
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X19Y25"
    )
    port map (
      IA => Slave_Mcompar_pstate_cmp_gt0000_cy_5_LOGIC_ONE_3736,
      IB => Slave_Mcompar_pstate_cmp_gt0000_cy_5_LOGIC_ONE_3736,
      SEL => Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYSELF_3726,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYMUXF2_3721
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X19Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_11_rt,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYSELF_3726
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_5_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYMUXFAST_3725,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_5_Q
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X19Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Mcompar_pstate_cmp_gt0000_cy_3_CYMUXFAST_3695,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_5_FASTCARRY_3723
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X19Y25"
    )
    port map (
      I0 => Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYSELG_3714,
      I1 => Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYSELF_3726,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYAND_3724
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X19Y25"
    )
    port map (
      IA => Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYMUXG2_3722,
      IB => Slave_Mcompar_pstate_cmp_gt0000_cy_5_FASTCARRY_3723,
      SEL => Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYAND_3724,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYMUXFAST_3725
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X19Y25"
    )
    port map (
      IA => Slave_Mcompar_pstate_cmp_gt0000_cy_5_LOGIC_ZERO_3720,
      IB => Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYMUXF2_3721,
      SEL => Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYSELG_3714,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYMUXG2_3722
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X19Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Mcompar_pstate_cmp_gt0000_lut_5_Q_3713,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_5_CYSELG_3714
    );
  Slave_ack_count_addsub0000_0_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X25Y30"
    )
    port map (
      O => Slave_ack_count_addsub0000_0_LOGIC_ZERO_3753
    );
  Slave_ack_count_addsub0000_0_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X25Y30"
    )
    port map (
      O => Slave_ack_count_addsub0000_0_LOGIC_ONE_3770
    );
  Slave_ack_count_addsub0000_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_0_XORF_3771,
      O => Slave_ack_count_addsub0000(0)
    );
  Slave_ack_count_addsub0000_0_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X25Y30"
    )
    port map (
      I0 => Slave_ack_count_addsub0000_0_CYINIT_3769,
      I1 => Slave_Madd_ack_count_addsub0000_lut(0),
      O => Slave_ack_count_addsub0000_0_XORF_3771
    );
  Slave_ack_count_addsub0000_0_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X25Y30"
    )
    port map (
      IA => Slave_ack_count_addsub0000_0_LOGIC_ONE_3770,
      IB => Slave_ack_count_addsub0000_0_CYINIT_3769,
      SEL => Slave_ack_count_addsub0000_0_CYSELF_3760,
      O => Slave_Madd_ack_count_addsub0000_cy_0_Q
    );
  Slave_ack_count_addsub0000_0_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X25Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => Slave_ack_count_addsub0000_0_CYINIT_3769
    );
  Slave_ack_count_addsub0000_0_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X25Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_ack_count_addsub0000_lut(0),
      O => Slave_ack_count_addsub0000_0_CYSELF_3760
    );
  Slave_ack_count_addsub0000_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_0_XORG_3756,
      O => Slave_ack_count_addsub0000(1)
    );
  Slave_ack_count_addsub0000_0_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X25Y30"
    )
    port map (
      I0 => Slave_Madd_ack_count_addsub0000_cy_0_Q,
      I1 => Slave_ack_count_addsub0000_0_G,
      O => Slave_ack_count_addsub0000_0_XORG_3756
    );
  Slave_ack_count_addsub0000_0_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_0_CYMUXG_3755,
      O => Slave_Madd_ack_count_addsub0000_cy_1_Q
    );
  Slave_ack_count_addsub0000_0_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X25Y30"
    )
    port map (
      IA => Slave_ack_count_addsub0000_0_LOGIC_ZERO_3753,
      IB => Slave_Madd_ack_count_addsub0000_cy_0_Q,
      SEL => Slave_ack_count_addsub0000_0_CYSELG_3744,
      O => Slave_ack_count_addsub0000_0_CYMUXG_3755
    );
  Slave_ack_count_addsub0000_0_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X25Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_0_G,
      O => Slave_ack_count_addsub0000_0_CYSELG_3744
    );
  Slave_ack_count_addsub0000_2_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X25Y31"
    )
    port map (
      O => Slave_ack_count_addsub0000_2_LOGIC_ZERO_3789
    );
  Slave_ack_count_addsub0000_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_2_XORF_3809,
      O => Slave_ack_count_addsub0000(2)
    );
  Slave_ack_count_addsub0000_2_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X25Y31"
    )
    port map (
      I0 => Slave_ack_count_addsub0000_2_CYINIT_3808,
      I1 => Slave_ack_count_addsub0000_2_F,
      O => Slave_ack_count_addsub0000_2_XORF_3809
    );
  Slave_ack_count_addsub0000_2_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X25Y31"
    )
    port map (
      IA => Slave_ack_count_addsub0000_2_LOGIC_ZERO_3789,
      IB => Slave_ack_count_addsub0000_2_CYINIT_3808,
      SEL => Slave_ack_count_addsub0000_2_CYSELF_3795,
      O => Slave_Madd_ack_count_addsub0000_cy_2_Q
    );
  Slave_ack_count_addsub0000_2_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X25Y31"
    )
    port map (
      IA => Slave_ack_count_addsub0000_2_LOGIC_ZERO_3789,
      IB => Slave_ack_count_addsub0000_2_LOGIC_ZERO_3789,
      SEL => Slave_ack_count_addsub0000_2_CYSELF_3795,
      O => Slave_ack_count_addsub0000_2_CYMUXF2_3790
    );
  Slave_ack_count_addsub0000_2_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X25Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_ack_count_addsub0000_cy_1_Q,
      O => Slave_ack_count_addsub0000_2_CYINIT_3808
    );
  Slave_ack_count_addsub0000_2_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X25Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_2_F,
      O => Slave_ack_count_addsub0000_2_CYSELF_3795
    );
  Slave_ack_count_addsub0000_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_2_XORG_3797,
      O => Slave_ack_count_addsub0000(3)
    );
  Slave_ack_count_addsub0000_2_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X25Y31"
    )
    port map (
      I0 => Slave_Madd_ack_count_addsub0000_cy_2_Q,
      I1 => Slave_ack_count_addsub0000_2_G,
      O => Slave_ack_count_addsub0000_2_XORG_3797
    );
  Slave_ack_count_addsub0000_2_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_2_CYMUXFAST_3794,
      O => Slave_Madd_ack_count_addsub0000_cy_3_Q
    );
  Slave_ack_count_addsub0000_2_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X25Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_ack_count_addsub0000_cy_1_Q,
      O => Slave_ack_count_addsub0000_2_FASTCARRY_3792
    );
  Slave_ack_count_addsub0000_2_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X25Y31"
    )
    port map (
      I0 => Slave_ack_count_addsub0000_2_CYSELG_3780,
      I1 => Slave_ack_count_addsub0000_2_CYSELF_3795,
      O => Slave_ack_count_addsub0000_2_CYAND_3793
    );
  Slave_ack_count_addsub0000_2_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X25Y31"
    )
    port map (
      IA => Slave_ack_count_addsub0000_2_CYMUXG2_3791,
      IB => Slave_ack_count_addsub0000_2_FASTCARRY_3792,
      SEL => Slave_ack_count_addsub0000_2_CYAND_3793,
      O => Slave_ack_count_addsub0000_2_CYMUXFAST_3794
    );
  Slave_ack_count_addsub0000_2_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X25Y31"
    )
    port map (
      IA => Slave_ack_count_addsub0000_2_LOGIC_ZERO_3789,
      IB => Slave_ack_count_addsub0000_2_CYMUXF2_3790,
      SEL => Slave_ack_count_addsub0000_2_CYSELG_3780,
      O => Slave_ack_count_addsub0000_2_CYMUXG2_3791
    );
  Slave_ack_count_addsub0000_2_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X25Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_2_G,
      O => Slave_ack_count_addsub0000_2_CYSELG_3780
    );
  Slave_ack_count_addsub0000_4_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X25Y32"
    )
    port map (
      O => Slave_ack_count_addsub0000_4_LOGIC_ZERO_3827
    );
  Slave_ack_count_addsub0000_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_4_XORF_3847,
      O => Slave_ack_count_addsub0000(4)
    );
  Slave_ack_count_addsub0000_4_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X25Y32"
    )
    port map (
      I0 => Slave_ack_count_addsub0000_4_CYINIT_3846,
      I1 => Slave_ack_count_addsub0000_4_F,
      O => Slave_ack_count_addsub0000_4_XORF_3847
    );
  Slave_ack_count_addsub0000_4_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X25Y32"
    )
    port map (
      IA => Slave_ack_count_addsub0000_4_LOGIC_ZERO_3827,
      IB => Slave_ack_count_addsub0000_4_CYINIT_3846,
      SEL => Slave_ack_count_addsub0000_4_CYSELF_3833,
      O => Slave_Madd_ack_count_addsub0000_cy_4_Q
    );
  Slave_ack_count_addsub0000_4_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X25Y32"
    )
    port map (
      IA => Slave_ack_count_addsub0000_4_LOGIC_ZERO_3827,
      IB => Slave_ack_count_addsub0000_4_LOGIC_ZERO_3827,
      SEL => Slave_ack_count_addsub0000_4_CYSELF_3833,
      O => Slave_ack_count_addsub0000_4_CYMUXF2_3828
    );
  Slave_ack_count_addsub0000_4_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X25Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_ack_count_addsub0000_cy_3_Q,
      O => Slave_ack_count_addsub0000_4_CYINIT_3846
    );
  Slave_ack_count_addsub0000_4_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X25Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_4_F,
      O => Slave_ack_count_addsub0000_4_CYSELF_3833
    );
  Slave_ack_count_addsub0000_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_4_XORG_3835,
      O => Slave_ack_count_addsub0000(5)
    );
  Slave_ack_count_addsub0000_4_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X25Y32"
    )
    port map (
      I0 => Slave_Madd_ack_count_addsub0000_cy_4_Q,
      I1 => Slave_ack_count_addsub0000_4_G,
      O => Slave_ack_count_addsub0000_4_XORG_3835
    );
  Slave_ack_count_addsub0000_4_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_4_CYMUXFAST_3832,
      O => Slave_Madd_ack_count_addsub0000_cy_5_Q
    );
  Slave_ack_count_addsub0000_4_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X25Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_ack_count_addsub0000_cy_3_Q,
      O => Slave_ack_count_addsub0000_4_FASTCARRY_3830
    );
  Slave_ack_count_addsub0000_4_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X25Y32"
    )
    port map (
      I0 => Slave_ack_count_addsub0000_4_CYSELG_3818,
      I1 => Slave_ack_count_addsub0000_4_CYSELF_3833,
      O => Slave_ack_count_addsub0000_4_CYAND_3831
    );
  Slave_ack_count_addsub0000_4_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X25Y32"
    )
    port map (
      IA => Slave_ack_count_addsub0000_4_CYMUXG2_3829,
      IB => Slave_ack_count_addsub0000_4_FASTCARRY_3830,
      SEL => Slave_ack_count_addsub0000_4_CYAND_3831,
      O => Slave_ack_count_addsub0000_4_CYMUXFAST_3832
    );
  Slave_ack_count_addsub0000_4_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X25Y32"
    )
    port map (
      IA => Slave_ack_count_addsub0000_4_LOGIC_ZERO_3827,
      IB => Slave_ack_count_addsub0000_4_CYMUXF2_3828,
      SEL => Slave_ack_count_addsub0000_4_CYSELG_3818,
      O => Slave_ack_count_addsub0000_4_CYMUXG2_3829
    );
  Slave_ack_count_addsub0000_4_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X25Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_4_G,
      O => Slave_ack_count_addsub0000_4_CYSELG_3818
    );
  Slave_ack_count_addsub0000_6_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X25Y33"
    )
    port map (
      O => Slave_ack_count_addsub0000_6_LOGIC_ZERO_3865
    );
  Slave_ack_count_addsub0000_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_6_XORF_3885,
      O => Slave_ack_count_addsub0000(6)
    );
  Slave_ack_count_addsub0000_6_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X25Y33"
    )
    port map (
      I0 => Slave_ack_count_addsub0000_6_CYINIT_3884,
      I1 => Slave_ack_count_addsub0000_6_F,
      O => Slave_ack_count_addsub0000_6_XORF_3885
    );
  Slave_ack_count_addsub0000_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X25Y33"
    )
    port map (
      IA => Slave_ack_count_addsub0000_6_LOGIC_ZERO_3865,
      IB => Slave_ack_count_addsub0000_6_CYINIT_3884,
      SEL => Slave_ack_count_addsub0000_6_CYSELF_3871,
      O => Slave_Madd_ack_count_addsub0000_cy_6_Q
    );
  Slave_ack_count_addsub0000_6_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X25Y33"
    )
    port map (
      IA => Slave_ack_count_addsub0000_6_LOGIC_ZERO_3865,
      IB => Slave_ack_count_addsub0000_6_LOGIC_ZERO_3865,
      SEL => Slave_ack_count_addsub0000_6_CYSELF_3871,
      O => Slave_ack_count_addsub0000_6_CYMUXF2_3866
    );
  Slave_ack_count_addsub0000_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X25Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_ack_count_addsub0000_cy_5_Q,
      O => Slave_ack_count_addsub0000_6_CYINIT_3884
    );
  Slave_ack_count_addsub0000_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X25Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_6_F,
      O => Slave_ack_count_addsub0000_6_CYSELF_3871
    );
  Slave_ack_count_addsub0000_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_6_XORG_3873,
      O => Slave_ack_count_addsub0000(7)
    );
  Slave_ack_count_addsub0000_6_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X25Y33"
    )
    port map (
      I0 => Slave_Madd_ack_count_addsub0000_cy_6_Q,
      I1 => Slave_ack_count_addsub0000_6_G,
      O => Slave_ack_count_addsub0000_6_XORG_3873
    );
  Slave_ack_count_addsub0000_6_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_6_CYMUXFAST_3870,
      O => Slave_Madd_ack_count_addsub0000_cy_7_Q
    );
  Slave_ack_count_addsub0000_6_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X25Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_ack_count_addsub0000_cy_5_Q,
      O => Slave_ack_count_addsub0000_6_FASTCARRY_3868
    );
  Slave_ack_count_addsub0000_6_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X25Y33"
    )
    port map (
      I0 => Slave_ack_count_addsub0000_6_CYSELG_3856,
      I1 => Slave_ack_count_addsub0000_6_CYSELF_3871,
      O => Slave_ack_count_addsub0000_6_CYAND_3869
    );
  Slave_ack_count_addsub0000_6_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X25Y33"
    )
    port map (
      IA => Slave_ack_count_addsub0000_6_CYMUXG2_3867,
      IB => Slave_ack_count_addsub0000_6_FASTCARRY_3868,
      SEL => Slave_ack_count_addsub0000_6_CYAND_3869,
      O => Slave_ack_count_addsub0000_6_CYMUXFAST_3870
    );
  Slave_ack_count_addsub0000_6_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X25Y33"
    )
    port map (
      IA => Slave_ack_count_addsub0000_6_LOGIC_ZERO_3865,
      IB => Slave_ack_count_addsub0000_6_CYMUXF2_3866,
      SEL => Slave_ack_count_addsub0000_6_CYSELG_3856,
      O => Slave_ack_count_addsub0000_6_CYMUXG2_3867
    );
  Slave_ack_count_addsub0000_6_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X25Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_6_G,
      O => Slave_ack_count_addsub0000_6_CYSELG_3856
    );
  Slave_ack_count_addsub0000_8_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X25Y34"
    )
    port map (
      O => Slave_ack_count_addsub0000_8_LOGIC_ZERO_3903
    );
  Slave_ack_count_addsub0000_8_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_8_XORF_3923,
      O => Slave_ack_count_addsub0000(8)
    );
  Slave_ack_count_addsub0000_8_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X25Y34"
    )
    port map (
      I0 => Slave_ack_count_addsub0000_8_CYINIT_3922,
      I1 => Slave_ack_count_addsub0000_8_F,
      O => Slave_ack_count_addsub0000_8_XORF_3923
    );
  Slave_ack_count_addsub0000_8_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X25Y34"
    )
    port map (
      IA => Slave_ack_count_addsub0000_8_LOGIC_ZERO_3903,
      IB => Slave_ack_count_addsub0000_8_CYINIT_3922,
      SEL => Slave_ack_count_addsub0000_8_CYSELF_3909,
      O => Slave_Madd_ack_count_addsub0000_cy_8_Q
    );
  Slave_ack_count_addsub0000_8_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X25Y34"
    )
    port map (
      IA => Slave_ack_count_addsub0000_8_LOGIC_ZERO_3903,
      IB => Slave_ack_count_addsub0000_8_LOGIC_ZERO_3903,
      SEL => Slave_ack_count_addsub0000_8_CYSELF_3909,
      O => Slave_ack_count_addsub0000_8_CYMUXF2_3904
    );
  Slave_ack_count_addsub0000_8_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X25Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_ack_count_addsub0000_cy_7_Q,
      O => Slave_ack_count_addsub0000_8_CYINIT_3922
    );
  Slave_ack_count_addsub0000_8_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X25Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_8_F,
      O => Slave_ack_count_addsub0000_8_CYSELF_3909
    );
  Slave_ack_count_addsub0000_8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_8_XORG_3911,
      O => Slave_ack_count_addsub0000(9)
    );
  Slave_ack_count_addsub0000_8_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X25Y34"
    )
    port map (
      I0 => Slave_Madd_ack_count_addsub0000_cy_8_Q,
      I1 => Slave_ack_count_addsub0000_8_G,
      O => Slave_ack_count_addsub0000_8_XORG_3911
    );
  Slave_ack_count_addsub0000_8_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X25Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_ack_count_addsub0000_cy_7_Q,
      O => Slave_ack_count_addsub0000_8_FASTCARRY_3906
    );
  Slave_ack_count_addsub0000_8_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X25Y34"
    )
    port map (
      I0 => Slave_ack_count_addsub0000_8_CYSELG_3894,
      I1 => Slave_ack_count_addsub0000_8_CYSELF_3909,
      O => Slave_ack_count_addsub0000_8_CYAND_3907
    );
  Slave_ack_count_addsub0000_8_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X25Y34"
    )
    port map (
      IA => Slave_ack_count_addsub0000_8_CYMUXG2_3905,
      IB => Slave_ack_count_addsub0000_8_FASTCARRY_3906,
      SEL => Slave_ack_count_addsub0000_8_CYAND_3907,
      O => Slave_ack_count_addsub0000_8_CYMUXFAST_3908
    );
  Slave_ack_count_addsub0000_8_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X25Y34"
    )
    port map (
      IA => Slave_ack_count_addsub0000_8_LOGIC_ZERO_3903,
      IB => Slave_ack_count_addsub0000_8_CYMUXF2_3904,
      SEL => Slave_ack_count_addsub0000_8_CYSELG_3894,
      O => Slave_ack_count_addsub0000_8_CYMUXG2_3905
    );
  Slave_ack_count_addsub0000_8_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X25Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_8_G,
      O => Slave_ack_count_addsub0000_8_CYSELG_3894
    );
  Slave_ack_count_addsub0000_10_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X25Y35"
    )
    port map (
      O => Slave_ack_count_addsub0000_10_LOGIC_ZERO_3953
    );
  Slave_ack_count_addsub0000_10_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_10_XORF_3954,
      O => Slave_ack_count_addsub0000(10)
    );
  Slave_ack_count_addsub0000_10_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X25Y35"
    )
    port map (
      I0 => Slave_ack_count_addsub0000_10_CYINIT_3952,
      I1 => Slave_ack_count_addsub0000_10_F,
      O => Slave_ack_count_addsub0000_10_XORF_3954
    );
  Slave_ack_count_addsub0000_10_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X25Y35"
    )
    port map (
      IA => Slave_ack_count_addsub0000_10_LOGIC_ZERO_3953,
      IB => Slave_ack_count_addsub0000_10_CYINIT_3952,
      SEL => Slave_ack_count_addsub0000_10_CYSELF_3943,
      O => Slave_Madd_ack_count_addsub0000_cy_10_Q
    );
  Slave_ack_count_addsub0000_10_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X25Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_8_CYMUXFAST_3908,
      O => Slave_ack_count_addsub0000_10_CYINIT_3952
    );
  Slave_ack_count_addsub0000_10_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X25Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_10_F,
      O => Slave_ack_count_addsub0000_10_CYSELF_3943
    );
  Slave_ack_count_addsub0000_10_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_addsub0000_10_XORG_3940,
      O => Slave_ack_count_addsub0000(11)
    );
  Slave_ack_count_addsub0000_10_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X25Y35"
    )
    port map (
      I0 => Slave_Madd_ack_count_addsub0000_cy_10_Q,
      I1 => Slave_ack_count_11_rt_3937,
      O => Slave_ack_count_addsub0000_10_XORG_3940
    );
  SW_1_IBUF : X_BUF
    generic map(
      LOC => "PAD117",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW(1),
      O => SW_1_INBUF
    );
  SW_1_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD117",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW_1_INBUF,
      O => SW_1_IBUF_1801
    );
  IMG1_ROW_EN_IBUF : X_BUF
    generic map(
      LOC => "PAD110",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_ROW_EN,
      O => IMG1_ROW_EN_INBUF
    );
  Slave_delay_count_share0000_4_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y19"
    )
    port map (
      O => Slave_delay_count_share0000_4_LOGIC_ZERO_3380
    );
  Slave_delay_count_share0000_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_4_XORF_3400,
      O => Slave_delay_count_share0000(4)
    );
  Slave_delay_count_share0000_4_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y19"
    )
    port map (
      I0 => Slave_delay_count_share0000_4_CYINIT_3399,
      I1 => Slave_delay_count_share0000_4_F,
      O => Slave_delay_count_share0000_4_XORF_3400
    );
  Slave_delay_count_share0000_4_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y19"
    )
    port map (
      IA => Slave_delay_count_share0000_4_LOGIC_ZERO_3380,
      IB => Slave_delay_count_share0000_4_CYINIT_3399,
      SEL => Slave_delay_count_share0000_4_CYSELF_3386,
      O => Slave_Madd_delay_count_share0000_cy_4_Q
    );
  Slave_delay_count_share0000_4_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y19"
    )
    port map (
      IA => Slave_delay_count_share0000_4_LOGIC_ZERO_3380,
      IB => Slave_delay_count_share0000_4_LOGIC_ZERO_3380,
      SEL => Slave_delay_count_share0000_4_CYSELF_3386,
      O => Slave_delay_count_share0000_4_CYMUXF2_3381
    );
  Slave_delay_count_share0000_4_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_delay_count_share0000_cy_3_Q,
      O => Slave_delay_count_share0000_4_CYINIT_3399
    );
  Slave_delay_count_share0000_4_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_4_F,
      O => Slave_delay_count_share0000_4_CYSELF_3386
    );
  Slave_delay_count_share0000_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_4_XORG_3388,
      O => Slave_delay_count_share0000(5)
    );
  Slave_delay_count_share0000_4_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y19"
    )
    port map (
      I0 => Slave_Madd_delay_count_share0000_cy_4_Q,
      I1 => Slave_delay_count_share0000_4_G,
      O => Slave_delay_count_share0000_4_XORG_3388
    );
  Slave_delay_count_share0000_4_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_4_CYMUXFAST_3385,
      O => Slave_Madd_delay_count_share0000_cy_5_Q
    );
  Slave_delay_count_share0000_4_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_delay_count_share0000_cy_3_Q,
      O => Slave_delay_count_share0000_4_FASTCARRY_3383
    );
  Slave_delay_count_share0000_4_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y19"
    )
    port map (
      I0 => Slave_delay_count_share0000_4_CYSELG_3371,
      I1 => Slave_delay_count_share0000_4_CYSELF_3386,
      O => Slave_delay_count_share0000_4_CYAND_3384
    );
  Slave_delay_count_share0000_4_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y19"
    )
    port map (
      IA => Slave_delay_count_share0000_4_CYMUXG2_3382,
      IB => Slave_delay_count_share0000_4_FASTCARRY_3383,
      SEL => Slave_delay_count_share0000_4_CYAND_3384,
      O => Slave_delay_count_share0000_4_CYMUXFAST_3385
    );
  Slave_delay_count_share0000_4_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y19"
    )
    port map (
      IA => Slave_delay_count_share0000_4_LOGIC_ZERO_3380,
      IB => Slave_delay_count_share0000_4_CYMUXF2_3381,
      SEL => Slave_delay_count_share0000_4_CYSELG_3371,
      O => Slave_delay_count_share0000_4_CYMUXG2_3382
    );
  Slave_delay_count_share0000_4_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_4_G,
      O => Slave_delay_count_share0000_4_CYSELG_3371
    );
  Slave_delay_count_share0000_6_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y20"
    )
    port map (
      O => Slave_delay_count_share0000_6_LOGIC_ZERO_3418
    );
  Slave_delay_count_share0000_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_6_XORF_3438,
      O => Slave_delay_count_share0000(6)
    );
  Slave_delay_count_share0000_6_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y20"
    )
    port map (
      I0 => Slave_delay_count_share0000_6_CYINIT_3437,
      I1 => Slave_delay_count_share0000_6_F,
      O => Slave_delay_count_share0000_6_XORF_3438
    );
  Slave_delay_count_share0000_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y20"
    )
    port map (
      IA => Slave_delay_count_share0000_6_LOGIC_ZERO_3418,
      IB => Slave_delay_count_share0000_6_CYINIT_3437,
      SEL => Slave_delay_count_share0000_6_CYSELF_3424,
      O => Slave_Madd_delay_count_share0000_cy_6_Q
    );
  Slave_delay_count_share0000_6_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y20"
    )
    port map (
      IA => Slave_delay_count_share0000_6_LOGIC_ZERO_3418,
      IB => Slave_delay_count_share0000_6_LOGIC_ZERO_3418,
      SEL => Slave_delay_count_share0000_6_CYSELF_3424,
      O => Slave_delay_count_share0000_6_CYMUXF2_3419
    );
  Slave_delay_count_share0000_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_delay_count_share0000_cy_5_Q,
      O => Slave_delay_count_share0000_6_CYINIT_3437
    );
  Slave_delay_count_share0000_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_6_F,
      O => Slave_delay_count_share0000_6_CYSELF_3424
    );
  Slave_delay_count_share0000_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_6_XORG_3426,
      O => Slave_delay_count_share0000(7)
    );
  Slave_delay_count_share0000_6_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y20"
    )
    port map (
      I0 => Slave_Madd_delay_count_share0000_cy_6_Q,
      I1 => Slave_delay_count_share0000_6_G,
      O => Slave_delay_count_share0000_6_XORG_3426
    );
  Slave_delay_count_share0000_6_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_6_CYMUXFAST_3423,
      O => Slave_Madd_delay_count_share0000_cy_7_Q
    );
  Slave_delay_count_share0000_6_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_delay_count_share0000_cy_5_Q,
      O => Slave_delay_count_share0000_6_FASTCARRY_3421
    );
  Slave_delay_count_share0000_6_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y20"
    )
    port map (
      I0 => Slave_delay_count_share0000_6_CYSELG_3409,
      I1 => Slave_delay_count_share0000_6_CYSELF_3424,
      O => Slave_delay_count_share0000_6_CYAND_3422
    );
  Slave_delay_count_share0000_6_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y20"
    )
    port map (
      IA => Slave_delay_count_share0000_6_CYMUXG2_3420,
      IB => Slave_delay_count_share0000_6_FASTCARRY_3421,
      SEL => Slave_delay_count_share0000_6_CYAND_3422,
      O => Slave_delay_count_share0000_6_CYMUXFAST_3423
    );
  Slave_delay_count_share0000_6_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y20"
    )
    port map (
      IA => Slave_delay_count_share0000_6_LOGIC_ZERO_3418,
      IB => Slave_delay_count_share0000_6_CYMUXF2_3419,
      SEL => Slave_delay_count_share0000_6_CYSELG_3409,
      O => Slave_delay_count_share0000_6_CYMUXG2_3420
    );
  Slave_delay_count_share0000_6_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_6_G,
      O => Slave_delay_count_share0000_6_CYSELG_3409
    );
  Slave_delay_count_share0000_8_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      O => Slave_delay_count_share0000_8_LOGIC_ZERO_3456
    );
  Slave_delay_count_share0000_8_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_8_XORF_3476,
      O => Slave_delay_count_share0000(8)
    );
  Slave_delay_count_share0000_8_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      I0 => Slave_delay_count_share0000_8_CYINIT_3475,
      I1 => Slave_delay_count_share0000_8_F,
      O => Slave_delay_count_share0000_8_XORF_3476
    );
  Slave_delay_count_share0000_8_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      IA => Slave_delay_count_share0000_8_LOGIC_ZERO_3456,
      IB => Slave_delay_count_share0000_8_CYINIT_3475,
      SEL => Slave_delay_count_share0000_8_CYSELF_3462,
      O => Slave_Madd_delay_count_share0000_cy_8_Q
    );
  Slave_delay_count_share0000_8_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      IA => Slave_delay_count_share0000_8_LOGIC_ZERO_3456,
      IB => Slave_delay_count_share0000_8_LOGIC_ZERO_3456,
      SEL => Slave_delay_count_share0000_8_CYSELF_3462,
      O => Slave_delay_count_share0000_8_CYMUXF2_3457
    );
  Slave_delay_count_share0000_8_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_delay_count_share0000_cy_7_Q,
      O => Slave_delay_count_share0000_8_CYINIT_3475
    );
  Slave_delay_count_share0000_8_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_8_F,
      O => Slave_delay_count_share0000_8_CYSELF_3462
    );
  Slave_delay_count_share0000_8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_8_XORG_3464,
      O => Slave_delay_count_share0000(9)
    );
  Slave_delay_count_share0000_8_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      I0 => Slave_Madd_delay_count_share0000_cy_8_Q,
      I1 => Slave_delay_count_share0000_8_G,
      O => Slave_delay_count_share0000_8_XORG_3464
    );
  Slave_delay_count_share0000_8_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_8_CYMUXFAST_3461,
      O => Slave_Madd_delay_count_share0000_cy_9_Q
    );
  Slave_delay_count_share0000_8_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_delay_count_share0000_cy_7_Q,
      O => Slave_delay_count_share0000_8_FASTCARRY_3459
    );
  Slave_delay_count_share0000_8_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      I0 => Slave_delay_count_share0000_8_CYSELG_3447,
      I1 => Slave_delay_count_share0000_8_CYSELF_3462,
      O => Slave_delay_count_share0000_8_CYAND_3460
    );
  Slave_delay_count_share0000_8_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      IA => Slave_delay_count_share0000_8_CYMUXG2_3458,
      IB => Slave_delay_count_share0000_8_FASTCARRY_3459,
      SEL => Slave_delay_count_share0000_8_CYAND_3460,
      O => Slave_delay_count_share0000_8_CYMUXFAST_3461
    );
  Slave_delay_count_share0000_8_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      IA => Slave_delay_count_share0000_8_LOGIC_ZERO_3456,
      IB => Slave_delay_count_share0000_8_CYMUXF2_3457,
      SEL => Slave_delay_count_share0000_8_CYSELG_3447,
      O => Slave_delay_count_share0000_8_CYMUXG2_3458
    );
  Slave_delay_count_share0000_8_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_8_G,
      O => Slave_delay_count_share0000_8_CYSELG_3447
    );
  Slave_delay_count_share0000_10_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      O => Slave_delay_count_share0000_10_LOGIC_ZERO_3494
    );
  Slave_delay_count_share0000_10_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_10_XORF_3514,
      O => Slave_delay_count_share0000(10)
    );
  Slave_delay_count_share0000_10_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      I0 => Slave_delay_count_share0000_10_CYINIT_3513,
      I1 => Slave_delay_count_share0000_10_F,
      O => Slave_delay_count_share0000_10_XORF_3514
    );
  Slave_delay_count_share0000_10_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      IA => Slave_delay_count_share0000_10_LOGIC_ZERO_3494,
      IB => Slave_delay_count_share0000_10_CYINIT_3513,
      SEL => Slave_delay_count_share0000_10_CYSELF_3500,
      O => Slave_Madd_delay_count_share0000_cy_10_Q
    );
  Slave_delay_count_share0000_10_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      IA => Slave_delay_count_share0000_10_LOGIC_ZERO_3494,
      IB => Slave_delay_count_share0000_10_LOGIC_ZERO_3494,
      SEL => Slave_delay_count_share0000_10_CYSELF_3500,
      O => Slave_delay_count_share0000_10_CYMUXF2_3495
    );
  Slave_delay_count_share0000_10_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_delay_count_share0000_cy_9_Q,
      O => Slave_delay_count_share0000_10_CYINIT_3513
    );
  Slave_delay_count_share0000_10_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_10_F,
      O => Slave_delay_count_share0000_10_CYSELF_3500
    );
  Slave_delay_count_share0000_10_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_10_XORG_3502,
      O => Slave_delay_count_share0000(11)
    );
  Slave_delay_count_share0000_10_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      I0 => Slave_Madd_delay_count_share0000_cy_10_Q,
      I1 => Slave_delay_count_share0000_10_G,
      O => Slave_delay_count_share0000_10_XORG_3502
    );
  Slave_delay_count_share0000_10_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_10_CYMUXFAST_3499,
      O => Slave_Madd_delay_count_share0000_cy_11_Q
    );
  Slave_delay_count_share0000_10_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_delay_count_share0000_cy_9_Q,
      O => Slave_delay_count_share0000_10_FASTCARRY_3497
    );
  Slave_delay_count_share0000_10_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      I0 => Slave_delay_count_share0000_10_CYSELG_3485,
      I1 => Slave_delay_count_share0000_10_CYSELF_3500,
      O => Slave_delay_count_share0000_10_CYAND_3498
    );
  Slave_delay_count_share0000_10_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      IA => Slave_delay_count_share0000_10_CYMUXG2_3496,
      IB => Slave_delay_count_share0000_10_FASTCARRY_3497,
      SEL => Slave_delay_count_share0000_10_CYAND_3498,
      O => Slave_delay_count_share0000_10_CYMUXFAST_3499
    );
  Slave_delay_count_share0000_10_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      IA => Slave_delay_count_share0000_10_LOGIC_ZERO_3494,
      IB => Slave_delay_count_share0000_10_CYMUXF2_3495,
      SEL => Slave_delay_count_share0000_10_CYSELG_3485,
      O => Slave_delay_count_share0000_10_CYMUXG2_3496
    );
  Slave_delay_count_share0000_10_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_10_G,
      O => Slave_delay_count_share0000_10_CYSELG_3485
    );
  Slave_delay_count_share0000_12_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      O => Slave_delay_count_share0000_12_LOGIC_ZERO_3532
    );
  Slave_delay_count_share0000_12_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_12_XORF_3552,
      O => Slave_delay_count_share0000(12)
    );
  Slave_delay_count_share0000_12_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      I0 => Slave_delay_count_share0000_12_CYINIT_3551,
      I1 => Slave_delay_count_share0000_12_F,
      O => Slave_delay_count_share0000_12_XORF_3552
    );
  Slave_delay_count_share0000_12_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      IA => Slave_delay_count_share0000_12_LOGIC_ZERO_3532,
      IB => Slave_delay_count_share0000_12_CYINIT_3551,
      SEL => Slave_delay_count_share0000_12_CYSELF_3538,
      O => Slave_Madd_delay_count_share0000_cy_12_Q
    );
  Slave_delay_count_share0000_12_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      IA => Slave_delay_count_share0000_12_LOGIC_ZERO_3532,
      IB => Slave_delay_count_share0000_12_LOGIC_ZERO_3532,
      SEL => Slave_delay_count_share0000_12_CYSELF_3538,
      O => Slave_delay_count_share0000_12_CYMUXF2_3533
    );
  Slave_delay_count_share0000_12_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_delay_count_share0000_cy_11_Q,
      O => Slave_delay_count_share0000_12_CYINIT_3551
    );
  Slave_delay_count_share0000_12_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_12_F,
      O => Slave_delay_count_share0000_12_CYSELF_3538
    );
  Slave_delay_count_share0000_12_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_12_XORG_3540,
      O => Slave_delay_count_share0000(13)
    );
  Slave_delay_count_share0000_12_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      I0 => Slave_Madd_delay_count_share0000_cy_12_Q,
      I1 => Slave_delay_count_share0000_12_G,
      O => Slave_delay_count_share0000_12_XORG_3540
    );
  Slave_delay_count_share0000_12_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_delay_count_share0000_cy_11_Q,
      O => Slave_delay_count_share0000_12_FASTCARRY_3535
    );
  Slave_delay_count_share0000_12_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      I0 => Slave_delay_count_share0000_12_CYSELG_3523,
      I1 => Slave_delay_count_share0000_12_CYSELF_3538,
      O => Slave_delay_count_share0000_12_CYAND_3536
    );
  Slave_delay_count_share0000_12_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      IA => Slave_delay_count_share0000_12_CYMUXG2_3534,
      IB => Slave_delay_count_share0000_12_FASTCARRY_3535,
      SEL => Slave_delay_count_share0000_12_CYAND_3536,
      O => Slave_delay_count_share0000_12_CYMUXFAST_3537
    );
  Slave_delay_count_share0000_12_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      IA => Slave_delay_count_share0000_12_LOGIC_ZERO_3532,
      IB => Slave_delay_count_share0000_12_CYMUXF2_3533,
      SEL => Slave_delay_count_share0000_12_CYSELG_3523,
      O => Slave_delay_count_share0000_12_CYMUXG2_3534
    );
  Slave_delay_count_share0000_12_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_12_G,
      O => Slave_delay_count_share0000_12_CYSELG_3523
    );
  Slave_delay_count_share0000_14_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y24"
    )
    port map (
      O => Slave_delay_count_share0000_14_LOGIC_ZERO_3582
    );
  Slave_delay_count_share0000_14_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_14_XORF_3583,
      O => Slave_delay_count_share0000(14)
    );
  Slave_delay_count_share0000_14_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y24"
    )
    port map (
      I0 => Slave_delay_count_share0000_14_CYINIT_3581,
      I1 => Slave_delay_count_share0000_14_F,
      O => Slave_delay_count_share0000_14_XORF_3583
    );
  Slave_delay_count_share0000_14_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y24"
    )
    port map (
      IA => Slave_delay_count_share0000_14_LOGIC_ZERO_3582,
      IB => Slave_delay_count_share0000_14_CYINIT_3581,
      SEL => Slave_delay_count_share0000_14_CYSELF_3572,
      O => Slave_Madd_delay_count_share0000_cy_14_Q
    );
  Slave_delay_count_share0000_14_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_12_CYMUXFAST_3537,
      O => Slave_delay_count_share0000_14_CYINIT_3581
    );
  Slave_delay_count_share0000_14_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_14_F,
      O => Slave_delay_count_share0000_14_CYSELF_3572
    );
  Slave_delay_count_share0000_14_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_share0000_14_XORG_3569,
      O => Slave_delay_count_share0000(15)
    );
  Slave_delay_count_share0000_14_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y24"
    )
    port map (
      I0 => Slave_Madd_delay_count_share0000_cy_14_Q,
      I1 => Slave_delay_count_15_rt_3566,
      O => Slave_delay_count_share0000_14_XORG_3569
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X19Y21"
    )
    port map (
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_LOGIC_ONE_3599
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X19Y21"
    )
    port map (
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_LOGIC_ZERO_3614
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X19Y21"
    )
    port map (
      IA => Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_LOGIC_ZERO_3614,
      IB => Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYINIT_3613,
      SEL => Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYSELF_3604,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_0_1
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X19Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYINIT_3613
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X19Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Mcompar_pstate_cmp_gt0000_lut_0_1,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYSELF_3604
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X19Y21"
    )
    port map (
      IA => Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_LOGIC_ONE_3599,
      IB => Slave_Mcompar_pstate_cmp_gt0000_cy_0_1,
      SEL => Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYSELG_3593,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYMUXG_3601
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X19Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Mcompar_pstate_cmp_gt0000_lut_1_1_3592,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYSELG_3593
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X19Y22"
    )
    port map (
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3632
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X19Y22"
    )
    port map (
      IA => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3632,
      IB => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3632,
      SEL => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYSELF_3638,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYMUXF2_3633
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X19Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Mcompar_pstate_cmp_gt0000_lut_2_1_3639,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYSELF_3638
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYMUXFAST_3637,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X19Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Mcompar_pstate_cmp_gt0000_cy_1_1_CYMUXG_3601,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_FASTCARRY_3635
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X19Y22"
    )
    port map (
      I0 => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYSELG_3625,
      I1 => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYSELF_3638,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYAND_3636
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X19Y22"
    )
    port map (
      IA => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYMUXG2_3634,
      IB => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_FASTCARRY_3635,
      SEL => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYAND_3636,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYMUXFAST_3637
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X19Y22"
    )
    port map (
      IA => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3632,
      IB => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYMUXF2_3633,
      SEL => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYSELG_3625,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYMUXG2_3634
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X19Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Mcompar_pstate_cmp_gt0000_lut_3_1_3624,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1_CYSELG_3625
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X19Y23"
    )
    port map (
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_1_LOGIC_ONE_3660
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X19Y23"
    )
    port map (
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_1_LOGIC_ZERO_3674
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X19Y23"
    )
    port map (
      IA => Slave_Mcompar_pstate_cmp_gt0000_cy_1_LOGIC_ZERO_3674,
      IB => Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYINIT_3673,
      SEL => Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYSELF_3665,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_0_Q
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X19Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYINIT_3673
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X19Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Mcompar_pstate_cmp_gt0000_lut_0_Q_3664,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYSELF_3665
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X19Y23"
    )
    port map (
      IA => Slave_Mcompar_pstate_cmp_gt0000_cy_1_LOGIC_ONE_3660,
      IB => Slave_Mcompar_pstate_cmp_gt0000_cy_0_Q,
      SEL => Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYSELG_3653,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYMUXG_3662
    );
  Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X19Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Mcompar_pstate_cmp_gt0000_lut_1_Q_3652,
      O => Slave_Mcompar_pstate_cmp_gt0000_cy_1_CYSELG_3653
    );
  IMG1_Data_6_IBUF : X_BUF
    generic map(
      LOC => "PAD93",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data(6),
      O => IMG1_Data_6_INBUF
    );
  IMG1_Data_6_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD93",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data_6_INBUF,
      O => IMG1_Data_6_IBUF_1814
    );
  LED_2_OBUF : X_OBUF
    generic map(
      LOC => "PAD120"
    )
    port map (
      I => LED_2_O,
      O => LED(2)
    );
  IMG1_Data_7_IBUF : X_BUF
    generic map(
      LOC => "PAD103",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data(7),
      O => IMG1_Data_7_INBUF
    );
  IMG1_Data_7_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD103",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data_7_INBUF,
      O => IMG1_Data_7_IBUF_1816
    );
  OEM_I2C_Clk_PULLUP : X_PU
    generic map(
      LOC => "PAD5"
    )
    port map (
      O => OEM_I2C_Clk
    );
  OEM_I2C_Clk_IBUF : X_BUF
    generic map(
      LOC => "PAD5",
      PATHPULSE => 798 ps
    )
    port map (
      I => OEM_I2C_Clk,
      O => OEM_I2C_Clk_INBUF
    );
  OEM_I2C_Clk_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD5",
      PATHPULSE => 798 ps
    )
    port map (
      I => OEM_I2C_Clk_INBUF,
      O => OEM_I2C_Clk_IBUF_1604
    );
  LED_3_OBUF : X_OBUF
    generic map(
      LOC => "PAD119"
    )
    port map (
      I => LED_3_O,
      O => LED(3)
    );
  IMG1_Data_8_IBUF : X_BUF
    generic map(
      LOC => "PAD104",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data(8),
      O => IMG1_Data_8_INBUF
    );
  IMG1_Data_8_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD104",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data_8_INBUF,
      O => IMG1_Data_8_IBUF_1818
    );
  IMG1_Data_9_IBUF : X_BUF
    generic map(
      LOC => "IPAD115",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data(9),
      O => IMG1_Data_9_INBUF
    );
  IMG1_Data_9_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD115",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data_9_INBUF,
      O => IMG1_Data_9_IBUF_1819
    );
  OEM_ROW_EN_OBUF : X_OBUF
    generic map(
      LOC => "PAD1"
    )
    port map (
      I => OEM_ROW_EN_O,
      O => OEM_ROW_EN
    );
  OEM_VSYNC_OBUF : X_OBUF
    generic map(
      LOC => "PAD172"
    )
    port map (
      I => OEM_VSYNC_O,
      O => OEM_VSYNC
    );
  OEM_PIXEL_Clk_OBUF : X_OBUF
    generic map(
      LOC => "PAD2"
    )
    port map (
      I => OEM_PIXEL_Clk_O,
      O => OEM_PIXEL_Clk
    );
  IMG1_I2C_Clk_PULLUP : X_PU
    generic map(
      LOC => "PAD113"
    )
    port map (
      O => IMG1_I2C_Clk
    );
  IMG1_I2C_Clk_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD113"
    )
    port map (
      I => IMG1_I2C_Clk_O,
      CTL => IMG1_I2C_Clk_T,
      O => IMG1_I2C_Clk
    );
  OEM_I2C_Data_PULLUP : X_PU
    generic map(
      LOC => "PAD7"
    )
    port map (
      O => OEM_I2C_Data
    );
  IOBUF_inst_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD7"
    )
    port map (
      I => OEM_I2C_Data_O,
      CTL => OEM_I2C_Data_T,
      O => OEM_I2C_Data
    );
  IOBUF_inst_IBUF : X_BUF
    generic map(
      LOC => "PAD7",
      PATHPULSE => 798 ps
    )
    port map (
      I => OEM_I2C_Data,
      O => OEM_I2C_Data_INBUF
    );
  OEM_I2C_Data_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD7",
      PATHPULSE => 798 ps
    )
    port map (
      I => OEM_I2C_Data_INBUF,
      O => oem_outI2Cdata
    );
  IMG0_VSYNC_IBUF : X_BUF
    generic map(
      LOC => "PAD20",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_VSYNC,
      O => IMG0_VSYNC_INBUF
    );
  IMG0_VSYNC_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD20",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_VSYNC_INBUF,
      O => IMG0_VSYNC_IBUF_1821
    );
  IMG0_RST_OBUF : X_OBUF
    generic map(
      LOC => "PAD25"
    )
    port map (
      I => IMG0_RST_O,
      O => IMG0_RST
    );
  IMG0_Data_0_IBUF : X_BUF
    generic map(
      LOC => "IPAD51",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data(0),
      O => IMG0_Data_0_INBUF
    );
  IMG0_Data_0_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD51",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data_0_INBUF,
      O => IMG0_Data_0_IBUF_1822
    );
  IMG0_Data_1_IBUF : X_BUF
    generic map(
      LOC => "IPAD45",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data(1),
      O => IMG0_Data_1_INBUF
    );
  IMG0_Data_1_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD45",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data_1_INBUF,
      O => IMG0_Data_1_IBUF_1823
    );
  IMG0_ROW_EN_IBUF : X_BUF
    generic map(
      LOC => "IPAD22",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_ROW_EN,
      O => IMG0_ROW_EN_INBUF
    );
  IMG0_ROW_EN_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD22",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_ROW_EN_INBUF,
      O => IMG0_ROW_EN_IBUF_1824
    );
  IMG0_I2C_Data_PULLUP : X_PU
    generic map(
      LOC => "PAD19"
    )
    port map (
      O => IMG0_I2C_Data
    );
  IMG0_I2C_Data_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD19"
    )
    port map (
      I => IMG0_I2C_Data_O,
      CTL => IMG0_I2C_Data_T,
      O => IMG0_I2C_Data
    );
  IMG0_Data_2_IBUF : X_BUF
    generic map(
      LOC => "IPAD44",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data(2),
      O => IMG0_Data_2_INBUF
    );
  IMG0_Data_2_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD44",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data_2_INBUF,
      O => IMG0_Data_2_IBUF_1825
    );
  IMG0_Data_3_IBUF : X_BUF
    generic map(
      LOC => "IPAD32",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data(3),
      O => IMG0_Data_3_INBUF
    );
  IMG0_Data_3_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD32",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data_3_INBUF,
      O => IMG0_Data_3_IBUF_1826
    );
  IMG0_Data_4_IBUF : X_BUF
    generic map(
      LOC => "PAD30",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data(4),
      O => IMG0_Data_4_INBUF
    );
  IMG0_Data_4_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD30",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data_4_INBUF,
      O => IMG0_Data_4_IBUF_1827
    );
  Clk_100MHz_BUFGP_IBUFG : X_BUF
    generic map(
      LOC => "PAD109",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz,
      O => Clk_100MHz_INBUF
    );
  IMG1_ROW_EN_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD110",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_ROW_EN_INBUF,
      O => IMG1_ROW_EN_IBUF_1802
    );
  SW_2_IBUF : X_BUF
    generic map(
      LOC => "PAD116",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW(2),
      O => SW_2_INBUF
    );
  SW_2_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD116",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW_2_INBUF,
      O => SW_2_IBUF_1803
    );
  IMG1_PIXEL_Clk_IBUF : X_BUF
    generic map(
      LOC => "PAD105",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_PIXEL_Clk,
      O => IMG1_PIXEL_Clk_INBUF
    );
  IMG1_PIXEL_Clk_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD105",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_PIXEL_Clk_INBUF,
      O => IMG1_PIXEL_Clk_IBUF_1804
    );
  SW_3_IBUF : X_BUF
    generic map(
      LOC => "IPAD21",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW(3),
      O => SW_3_INBUF
    );
  SW_3_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD21",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW_3_INBUF,
      O => SW_3_IBUF_1805
    );
  OEM_Data_0_OBUF : X_OBUF
    generic map(
      LOC => "PAD159"
    )
    port map (
      I => OEM_Data_0_O,
      O => OEM_Data(0)
    );
  OEM_Data_1_OBUF : X_OBUF
    generic map(
      LOC => "PAD160"
    )
    port map (
      I => OEM_Data_1_O,
      O => OEM_Data(1)
    );
  OEM_Data_2_OBUF : X_OBUF
    generic map(
      LOC => "PAD161"
    )
    port map (
      I => OEM_Data_2_O,
      O => OEM_Data(2)
    );
  OEM_Data_3_OBUF : X_OBUF
    generic map(
      LOC => "PAD163"
    )
    port map (
      I => OEM_Data_3_O,
      O => OEM_Data(3)
    );
  OEM_Data_4_OBUF : X_OBUF
    generic map(
      LOC => "PAD164"
    )
    port map (
      I => OEM_Data_4_O,
      O => OEM_Data(4)
    );
  OEM_Data_5_OBUF : X_OBUF
    generic map(
      LOC => "PAD165"
    )
    port map (
      I => OEM_Data_5_O,
      O => OEM_Data(5)
    );
  OEM_Data_6_OBUF : X_OBUF
    generic map(
      LOC => "PAD166"
    )
    port map (
      I => OEM_Data_6_O,
      O => OEM_Data(6)
    );
  IMG1_Data_0_IBUF : X_BUF
    generic map(
      LOC => "PAD94",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data(0),
      O => IMG1_Data_0_INBUF
    );
  IMG1_Data_0_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD94",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data_0_INBUF,
      O => IMG1_Data_0_IBUF_1806
    );
  OEM_Data_7_OBUF : X_OBUF
    generic map(
      LOC => "PAD169"
    )
    port map (
      I => OEM_Data_7_O,
      O => OEM_Data(7)
    );
  IMG1_Data_1_IBUF : X_BUF
    generic map(
      LOC => "PAD97",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data(1),
      O => IMG1_Data_1_INBUF
    );
  IMG1_Data_1_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD97",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data_1_INBUF,
      O => IMG1_Data_1_IBUF_1807
    );
  OEM_Data_8_OBUF : X_OBUF
    generic map(
      LOC => "PAD170"
    )
    port map (
      I => OEM_Data_8_O,
      O => OEM_Data(8)
    );
  IMG1_Data_2_IBUF : X_BUF
    generic map(
      LOC => "PAD98",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data(2),
      O => IMG1_Data_2_INBUF
    );
  IMG1_Data_2_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD98",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data_2_INBUF,
      O => IMG1_Data_2_IBUF_1808
    );
  IMG1_VSYNC_IBUF : X_BUF
    generic map(
      LOC => "IPAD114",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_VSYNC,
      O => IMG1_VSYNC_INBUF
    );
  IMG1_VSYNC_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD114",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_VSYNC_INBUF,
      O => IMG1_VSYNC_IBUF_1809
    );
  OEM_Data_9_OBUF : X_OBUF
    generic map(
      LOC => "PAD171"
    )
    port map (
      I => OEM_Data_9_O,
      O => OEM_Data(9)
    );
  IMG1_Data_3_IBUF : X_BUF
    generic map(
      LOC => "PAD100",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data(3),
      O => IMG1_Data_3_INBUF
    );
  IMG1_Data_3_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD100",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data_3_INBUF,
      O => IMG1_Data_3_IBUF_1810
    );
  IMG1_Data_4_IBUF : X_BUF
    generic map(
      LOC => "PAD101",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data(4),
      O => IMG1_Data_4_INBUF
    );
  IMG1_Data_4_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD101",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data_4_INBUF,
      O => IMG1_Data_4_IBUF_1811
    );
  LED_0_OBUF : X_OBUF
    generic map(
      LOC => "PAD122"
    )
    port map (
      I => LED_0_O,
      O => LED(0)
    );
  IMG1_Data_5_IBUF : X_BUF
    generic map(
      LOC => "PAD102",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data(5),
      O => IMG1_Data_5_INBUF
    );
  IMG1_Data_5_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD102",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG1_Data_5_INBUF,
      O => IMG1_Data_5_IBUF_1813
    );
  LED_1_OBUF : X_OBUF
    generic map(
      LOC => "PAD121"
    )
    port map (
      I => LED_1_O,
      O => LED(1)
    );
  IMG0_Data_5_IBUF : X_BUF
    generic map(
      LOC => "IPAD29",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data(5),
      O => IMG0_Data_5_INBUF
    );
  IMG0_Data_5_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD29",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data_5_INBUF,
      O => IMG0_Data_5_IBUF_1829
    );
  IMG1_RST_OBUF : X_OBUF
    generic map(
      LOC => "PAD111"
    )
    port map (
      I => IMG1_RST_O,
      O => IMG1_RST
    );
  IMG1_I2C_Data_PULLUP : X_PU
    generic map(
      LOC => "PAD112"
    )
    port map (
      O => IMG1_I2C_Data
    );
  IMG1_I2C_Data_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD112"
    )
    port map (
      I => IMG1_I2C_Data_O,
      CTL => IMG1_I2C_Data_T,
      O => IMG1_I2C_Data
    );
  IMG0_Data_6_IBUF : X_BUF
    generic map(
      LOC => "IPAD28",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data(6),
      O => IMG0_Data_6_INBUF
    );
  IMG0_Data_6_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD28",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data_6_INBUF,
      O => IMG0_Data_6_IBUF_1830
    );
  IMG0_Data_7_IBUF : X_BUF
    generic map(
      LOC => "PAD26",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data(7),
      O => IMG0_Data_7_INBUF
    );
  IMG0_Data_7_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD26",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data_7_INBUF,
      O => IMG0_Data_7_IBUF_1831
    );
  IMG0_Data_8_IBUF : X_BUF
    generic map(
      LOC => "IPAD13",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data(8),
      O => IMG0_Data_8_INBUF
    );
  IMG0_Data_8_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD13",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data_8_INBUF,
      O => IMG0_Data_8_IBUF_1832
    );
  IMG0_Data_9_IBUF : X_BUF
    generic map(
      LOC => "IPAD3",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data(9),
      O => IMG0_Data_9_INBUF
    );
  IMG0_Data_9_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD3",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_Data_9_INBUF,
      O => IMG0_Data_9_IBUF_1833
    );
  IMG0_PIXEL_Clk_IBUF : X_BUF
    generic map(
      LOC => "PAD24",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_PIXEL_Clk,
      O => IMG0_PIXEL_Clk_INBUF
    );
  IMG0_PIXEL_Clk_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD24",
      PATHPULSE => 798 ps
    )
    port map (
      I => IMG0_PIXEL_Clk_INBUF,
      O => IMG0_PIXEL_Clk_IBUF_1834
    );
  SW_0_IBUF : X_BUF
    generic map(
      LOC => "PAD124",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW(0),
      O => SW_0_INBUF
    );
  SW_0_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD124",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW_0_INBUF,
      O => SW_0_IBUF_1835
    );
  IMG0_I2C_Clk_PULLUP : X_PU
    generic map(
      LOC => "PAD18"
    )
    port map (
      O => IMG0_I2C_Clk
    );
  IMG0_I2C_Clk_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD18"
    )
    port map (
      I => IMG0_I2C_Clk_O,
      CTL => IMG0_I2C_Clk_T,
      O => IMG0_I2C_Clk
    );
  Clk_100MHz_BUFGP_BUFG : X_BUFGMUX
    generic map(
      LOC => "BUFGMUX_X1Y0"
    )
    port map (
      I0 => Clk_100MHz_BUFGP_BUFG_I0_INV,
      I1 => GND,
      S => Clk_100MHz_BUFGP_BUFG_S_INVNOT,
      O => Clk_100MHz_BUFGP
    );
  Clk_100MHz_BUFGP_BUFG_SINV : X_INV
    generic map(
      LOC => "BUFGMUX_X1Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => Clk_100MHz_BUFGP_BUFG_S_INVNOT
    );
  Clk_100MHz_BUFGP_BUFG_I0_USED : X_BUF
    generic map(
      LOC => "BUFGMUX_X1Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_INBUF,
      O => Clk_100MHz_BUFGP_BUFG_I0_INV
    );
  Slave_pstate_FFd2_In26_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X16Y37"
    )
    port map (
      IA => N182,
      IB => N183,
      SEL => Slave_pstate_FFd2_In26_BXINV_4406,
      O => Slave_pstate_FFd2_In26_F5MUX_4413
    );
  Slave_pstate_FFd2_In26_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd2_In9_2724,
      O => Slave_pstate_FFd2_In26_BXINV_4406
    );
  Slave_pstate_FFd3_In103_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X14Y37"
    )
    port map (
      IA => N186,
      IB => N187,
      SEL => Slave_pstate_FFd3_In103_BXINV_4431,
      O => Slave_pstate_FFd3_In103_F5MUX_4438
    );
  Slave_pstate_FFd3_In103_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X14Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => N60,
      O => Slave_pstate_FFd3_In103_BXINV_4431
    );
  Slave_pstate_FFd3_In103_G : X_LUT4
    generic map(
      INIT => X"FCFE",
      LOC => "SLICE_X14Y37"
    )
    port map (
      ADR0 => Slave_nstate_FFd2_1691,
      ADR1 => Slave_pstate_FFd3_In28_0,
      ADR2 => Slave_nstate_FFd3_1642,
      ADR3 => Slave_Mcompar_pstate_cmp_gt0000_cy_5_Q,
      O => N187
    );
  N111_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => N111_F5MUX_4463,
      O => N111
    );
  N111_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X18Y37"
    )
    port map (
      IA => N163,
      IB => N164,
      SEL => N111_BXINV_4456,
      O => N111_F5MUX_4463
    );
  N111_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X18Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N18_0,
      O => N111_BXINV_4456
    );
  Slave_delay_count_mux0000_0_182_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000_0_182_F5MUX_4488,
      O => Slave_delay_count_mux0000_0_182
    );
  Slave_delay_count_mux0000_0_182_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X19Y20"
    )
    port map (
      IA => N184,
      IB => N185,
      SEL => Slave_delay_count_mux0000_0_182_BXINV_4481,
      O => Slave_delay_count_mux0000_0_182_F5MUX_4488
    );
  Slave_delay_count_mux0000_0_182_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X19Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count(11),
      O => Slave_delay_count_mux0000_0_182_BXINV_4481
    );
  Slave_counter_4_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X14Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_4_F5MUX_4515,
      O => Slave_counter_4_DXMUX_4517
    );
  Slave_counter_4_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X14Y28"
    )
    port map (
      IA => N165,
      IB => N166,
      SEL => Slave_counter_4_BXINV_4508,
      O => Slave_counter_4_F5MUX_4515
    );
  Slave_counter_4_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X14Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Madd_counter_addsub0000_cy(3),
      O => Slave_counter_4_BXINV_4508
    );
  Slave_counter_4_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X14Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_counter_4_CLKINV_4501
    );
  Slave_counter_mux0000_1_F : X_LUT4
    generic map(
      INIT => X"F0E0",
      LOC => "SLICE_X14Y28"
    )
    port map (
      ADR0 => Slave_N18_0,
      ADR1 => Slave_nstate_FFd3_1642,
      ADR2 => Slave_counter(4),
      ADR3 => Slave_nstate_FFd2_1691,
      O => N165
    );
  Slave_nstate_FFd6_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X17Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd6_FXMUX_4547,
      O => Slave_nstate_FFd6_DXMUX_4548
    );
  Slave_nstate_FFd6_FXMUX : X_BUF
    generic map(
      LOC => "SLICE_X17Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd6_In,
      O => Slave_nstate_FFd6_FXMUX_4547
    );
  Slave_nstate_FFd6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd6_In2_SW1_O_pack_1,
      O => Slave_nstate_FFd6_In2_SW1_O
    );
  Slave_nstate_FFd6_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X17Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_nstate_FFd6_CLKINV_4533
    );
  Slave_nstate_FFd6_In2_SW1 : X_LUT4
    generic map(
      INIT => X"FFF7",
      LOC => "SLICE_X17Y30"
    )
    port map (
      ADR0 => Slave_nstate_FFd1_1598,
      ADR1 => Slave_counter(1),
      ADR2 => Slave_counter(2),
      ADR3 => Slave_counter(0),
      O => Slave_nstate_FFd6_In2_SW1_O_pack_1
    );
  Slave_delay_count_cmp_eq0000_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_cmp_eq0000,
      O => Slave_delay_count_cmp_eq0000_0
    );
  Slave_delay_count_cmp_eq0000_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg_cmp_eq0000232_O_pack_1,
      O => Slave_shiftReg_cmp_eq0000232_O
    );
  Slave_shiftReg_cmp_eq0000232 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X20Y20"
    )
    port map (
      ADR0 => Slave_delay_count(2),
      ADR1 => Slave_delay_count(11),
      ADR2 => Slave_delay_count(9),
      ADR3 => Slave_delay_count(3),
      O => Slave_shiftReg_cmp_eq0000232_O_pack_1
    );
  Slave_N38_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N38,
      O => Slave_N38_0
    );
  Slave_N38_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => N86_pack_1,
      O => N86
    );
  Slave_pstate_FFd2_In159_SW1 : X_LUT4
    generic map(
      INIT => X"FFEF",
      LOC => "SLICE_X15Y32"
    )
    port map (
      ADR0 => Slave_counter(3),
      ADR1 => Slave_counter(2),
      ADR2 => Slave_counter(1),
      ADR3 => Slave_counter(0),
      O => N86_pack_1
    );
  Slave_doutvalid_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_doutvalid_mux000057,
      O => Slave_doutvalid_DXMUX_4628
    );
  Slave_doutvalid_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_doutvalid_mux0000211_O_pack_1,
      O => Slave_doutvalid_mux0000211_O
    );
  Slave_doutvalid_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd6_FXMUX_4547,
      O => Slave_doutvalid_SRINV_4613
    );
  Slave_doutvalid_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_doutvalid_CLKINV_4612
    );
  Slave_counter_0_1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_0_1_FXMUX_4661,
      O => Slave_counter_0_1_DXMUX_4662
    );
  Slave_counter_0_1_FXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_mux0000_5_45,
      O => Slave_counter_0_1_FXMUX_4661
    );
  Slave_counter_0_1_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_mux0000_5_29_O_pack_1,
      O => Slave_counter_mux0000_5_29_O
    );
  Slave_counter_0_1_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_mux0000_5_13_0,
      O => Slave_counter_0_1_SRINV_4646
    );
  Slave_counter_0_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_counter_0_1_CLKINV_4645
    );
  N30_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N34_pack_1,
      O => Slave_N34
    );
  Slave_shiftReg_mux0001_0_2 : X_LUT4
    generic map(
      INIT => X"F070",
      LOC => "SLICE_X20Y39"
    )
    port map (
      ADR0 => Slave_delay_count_cmp_eq0000_0,
      ADR1 => Slave_N36_0,
      ADR2 => N28_0,
      ADR3 => Slave_delay_count(5),
      O => Slave_N34_pack_1
    );
  Slave_pstate_FFd2_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X14Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd2_In245,
      O => Slave_pstate_FFd2_DXMUX_4719
    );
  Slave_pstate_FFd2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd2_In91_O_pack_1,
      O => Slave_pstate_FFd2_In91_O
    );
  Slave_pstate_FFd2_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X14Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd2_In26_F5MUX_4413,
      O => Slave_pstate_FFd2_SRINV_4704
    );
  Slave_pstate_FFd2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X14Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_pstate_FFd2_CLKINV_4703
    );
  Slave_pstate_FFd1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X14Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd1_In40,
      O => Slave_pstate_FFd1_DXMUX_4752
    );
  Slave_pstate_FFd1_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd1_In26_O_pack_1,
      O => Slave_pstate_FFd1_In26_O
    );
  Slave_pstate_FFd1_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X14Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd1_In15_5564,
      O => Slave_pstate_FFd1_SRINV_4737
    );
  Slave_pstate_FFd1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X14Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_pstate_FFd1_CLKINV_4736
    );
  Slave_N391_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N391,
      O => Slave_N391_0
    );
  Slave_N391_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => N56_pack_1,
      O => N56
    );
  Slave_pstate_FFd2_In33_SW0 : X_LUT4
    generic map(
      INIT => X"EEEE",
      LOC => "SLICE_X14Y30"
    )
    port map (
      ADR0 => Slave_counter(4),
      ADR1 => Slave_counter(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => N56_pack_1
    );
  N60_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd3_In50_O_pack_1,
      O => Slave_pstate_FFd3_In50_O
    );
  Slave_pstate_FFd3_In50 : X_LUT4
    generic map(
      INIT => X"8844",
      LOC => "SLICE_X15Y35"
    )
    port map (
      ADR0 => Slave_counter(0),
      ADR1 => Slave_counter_and0000,
      ADR2 => VCC,
      ADR3 => Slave_counter(3),
      O => Slave_pstate_FFd3_In50_O_pack_1
    );
  Slave_pstate_FFd3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X15Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd3_In122,
      O => Slave_pstate_FFd3_DXMUX_4833
    );
  Slave_pstate_FFd3_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd1_In1313_pack_1,
      O => Slave_pstate_FFd1_In1313_1858
    );
  Slave_pstate_FFd3_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd3_In103_F5MUX_4438,
      O => Slave_pstate_FFd3_SRINV_4818
    );
  Slave_pstate_FFd3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_pstate_FFd3_CLKINV_4817
    );
  Slave_N40_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N40,
      O => Slave_N40_0
    );
  Slave_N40_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_cmp_eq0000_pack_1,
      O => Slave_ack_count_cmp_eq0000_1679
    );
  Slave_ack_count_cmp_eq0000 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X22Y33"
    )
    port map (
      ADR0 => Slave_ack_count(9),
      ADR1 => N94_0,
      ADR2 => N48,
      ADR3 => N12_0,
      O => Slave_ack_count_cmp_eq0000_pack_1
    );
  N88_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => N88,
      O => N88_0
    );
  N88_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N291_pack_1,
      O => Slave_N291
    );
  Slave_Dir_mux0000141 : X_LUT4
    generic map(
      INIT => X"FFFC",
      LOC => "SLICE_X20Y32"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_N32,
      ADR2 => Slave_nstate_FFd3_1642,
      ADR3 => Slave_nstate_FFd4_1597,
      O => Slave_N291_pack_1
    );
  Slave_Dir_mux00002_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Dir_mux00002,
      O => Slave_Dir_mux00002_0
    );
  Slave_Dir_mux00002_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N45_pack_1,
      O => Slave_N45
    );
  Slave_Dir_mux000022 : X_LUT4
    generic map(
      INIT => X"8080",
      LOC => "SLICE_X23Y33"
    )
    port map (
      ADR0 => Slave_ack_count(6),
      ADR1 => Slave_ack_count(5),
      ADR2 => Slave_ack_count(8),
      ADR3 => VCC,
      O => Slave_N45_pack_1
    );
  Slave_Dir_mux000051_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Dir_mux000039_SW0_O_pack_1,
      O => Slave_Dir_mux000039_SW0_O
    );
  Slave_Dir_mux000039_SW0 : X_LUT4
    generic map(
      INIT => X"8800",
      LOC => "SLICE_X20Y26"
    )
    port map (
      ADR0 => Slave_Dir_mux000016_0,
      ADR1 => Slave_Dir_mux000025_0,
      ADR2 => VCC,
      ADR3 => Slave_Dir_mux000030_0,
      O => Slave_Dir_mux000039_SW0_O_pack_1
    );
  Slave_N18_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N18,
      O => Slave_N18_0
    );
  Slave_N18_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N32_pack_1,
      O => Slave_N32
    );
  Slave_Dir_mux0000121 : X_LUT4
    generic map(
      INIT => X"FFEE",
      LOC => "SLICE_X18Y31"
    )
    port map (
      ADR0 => Slave_nstate_FFd5_1646,
      ADR1 => Slave_nstate_FFd6_1709,
      ADR2 => VCC,
      ADR3 => Slave_nstate_FFd7_1710,
      O => Slave_N32_pack_1
    );
  Slave_N17_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N17,
      O => Slave_N17_0
    );
  Slave_N17_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_or0000_pack_1,
      O => Slave_delay_count_or0000_1625
    );
  Slave_delay_count_or0000 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X21Y31"
    )
    port map (
      ADR0 => Slave_nstate_FFd3_1642,
      ADR1 => Slave_nstate_FFd6_1709,
      ADR2 => Slave_nstate_FFd5_1646,
      ADR3 => N2_0,
      O => Slave_delay_count_or0000_pack_1
    );
  N25_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => N25,
      O => N25_0
    );
  N25_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N39_pack_1,
      O => Slave_N39
    );
  Slave_counter_mux0000_4_31 : X_LUT4
    generic map(
      INIT => X"A0A0",
      LOC => "SLICE_X14Y31"
    )
    port map (
      ADR0 => Slave_nstate_FFd3_1642,
      ADR1 => VCC,
      ADR2 => Slave_ClkRisingEdge_1699,
      ADR3 => VCC,
      O => Slave_N39_pack_1
    );
  Slave_delay_count_0_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X18Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000_0_1_5031,
      O => Slave_delay_count_0_DXMUX_5034
    );
  Slave_delay_count_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N3_pack_1,
      O => Slave_N3
    );
  Slave_delay_count_0_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X18Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => N50,
      O => Slave_delay_count_0_SRINV_5017
    );
  Slave_delay_count_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X18Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_delay_count_0_CLKINV_5016
    );
  Slave_delay_count_mux0000_0_1123 : X_LUT4
    generic map(
      INIT => X"FEAA",
      LOC => "SLICE_X18Y21"
    )
    port map (
      ADR0 => Slave_nstate_FFd7_1710,
      ADR1 => Slave_delay_count_mux0000_0_111_0,
      ADR2 => Slave_delay_count_mux0000_0_182,
      ADR3 => Slave_nstate_FFd2_1691,
      O => Slave_N3_pack_1
    );
  Slave_pstate_cmp_eq0002_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_cmp_eq0002_5060,
      O => Slave_pstate_cmp_eq0002_0
    );
  Slave_pstate_cmp_eq0002_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => N52_pack_1,
      O => N52
    );
  Slave_pstate_cmp_eq0010_SW0 : X_LUT4
    generic map(
      INIT => X"FFBB",
      LOC => "SLICE_X17Y32"
    )
    port map (
      ADR0 => Slave_counter(2),
      ADR1 => Slave_counter(3),
      ADR2 => VCC,
      ADR3 => Slave_counter_0_1_1851,
      O => N52_pack_1
    );
  Slave_nstate_FFd2_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X17Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd2_In_5086,
      O => Slave_nstate_FFd2_DXMUX_5089
    );
  Slave_nstate_FFd2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N46_pack_1,
      O => Slave_N46
    );
  Slave_nstate_FFd2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X17Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_nstate_FFd2_CLKINV_5072
    );
  Slave_pstate_FFd2_In81 : X_LUT4
    generic map(
      INIT => X"AA00",
      LOC => "SLICE_X17Y35"
    )
    port map (
      ADR0 => Slave_pstate_cmp_eq0008_0,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Slave_nstate_FFd1_1598,
      O => Slave_N46_pack_1
    );
  Slave_pstate_cmp_eq0008_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_cmp_eq0008_5114,
      O => Slave_pstate_cmp_eq0008_0
    );
  Slave_pstate_cmp_eq0008_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_cmp_eq0008_SW1_O_pack_1,
      O => Slave_pstate_cmp_eq0008_SW1_O
    );
  Slave_pstate_cmp_eq0008_SW1 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X23Y32"
    )
    port map (
      ADR0 => Slave_ack_count(1),
      ADR1 => Slave_ack_count(0),
      ADR2 => Slave_ack_count(11),
      ADR3 => Slave_ack_count(10),
      O => Slave_pstate_cmp_eq0008_SW1_O_pack_1
    );
  Slave_nstate_FFd1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X15Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd1_In27,
      O => Slave_nstate_FFd1_DXMUX_5145
    );
  Slave_nstate_FFd1_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd1_In8_O_pack_1,
      O => Slave_nstate_FFd1_In8_O
    );
  Slave_nstate_FFd1_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd1_In0_2741,
      O => Slave_nstate_FFd1_SRINV_5130
    );
  Slave_nstate_FFd1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_nstate_FFd1_CLKINV_5129
    );
  Slave_N401_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N401,
      O => Slave_N401_0
    );
  Slave_N401_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => N130_pack_1,
      O => N130
    );
  Slave_pstate_FFd2_In65_SW0 : X_LUT4
    generic map(
      INIT => X"C7FD",
      LOC => "SLICE_X14Y35"
    )
    port map (
      ADR0 => Slave_counter(3),
      ADR1 => Slave_counter(1),
      ADR2 => Slave_counter(0),
      ADR3 => Slave_counter(4),
      O => N130_pack_1
    );
  Slave_pstate_FFd3_In28_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd3_In28_5195,
      O => Slave_pstate_FFd3_In28_0
    );
  Slave_pstate_FFd3_In28_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd3_In21_SW1_O_pack_1,
      O => Slave_pstate_FFd3_In21_SW1_O
    );
  Slave_pstate_FFd3_In21_SW1 : X_LUT4
    generic map(
      INIT => X"AAA8",
      LOC => "SLICE_X15Y39"
    )
    port map (
      ADR0 => N107_0,
      ADR1 => Slave_nstate_FFd7_1710,
      ADR2 => Slave_nstate_FFd2_1691,
      ADR3 => Slave_nstate_FFd3_1642,
      O => Slave_pstate_FFd3_In21_SW1_O_pack_1
    );
  Slave_ack_count_9_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X23Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_mux0000(9),
      O => Slave_ack_count_9_DXMUX_5224
    );
  Slave_ack_count_9_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N0_pack_1,
      O => Slave_N0
    );
  Slave_ack_count_9_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X23Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_ack_count_9_CLKINV_5209
    );
  Slave_ack_count_mux0000_10_1 : X_LUT4
    generic map(
      INIT => X"FFF8",
      LOC => "SLICE_X23Y31"
    )
    port map (
      ADR0 => Slave_ack_count_cmp_eq0000_1679,
      ADR1 => N8_0,
      ADR2 => Slave_N28_0,
      ADR3 => Slave_nstate_FFd4_1597,
      O => Slave_N0_pack_1
    );
  Slave_nstate_FFd3_In41_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd3_In15_O_pack_1,
      O => Slave_nstate_FFd3_In15_O
    );
  Slave_nstate_FFd3_In15 : X_LUT4
    generic map(
      INIT => X"FEF2",
      LOC => "SLICE_X16Y35"
    )
    port map (
      ADR0 => Slave_pstate_cmp_eq0010_0,
      ADR1 => N105_0,
      ADR2 => Slave_pstate_cmp_eq0002_0,
      ADR3 => Slave_counter(3),
      O => Slave_nstate_FFd3_In15_O_pack_1
    );
  Slave_nstate_FFd4_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd4_In79,
      O => Slave_nstate_FFd4_DXMUX_5280
    );
  Slave_nstate_FFd4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd4_In54_SW0_O_pack_1,
      O => Slave_nstate_FFd4_In54_SW0_O
    );
  Slave_nstate_FFd4_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd4_In19_5903,
      O => Slave_nstate_FFd4_SRINV_5265
    );
  Slave_nstate_FFd4_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_nstate_FFd4_CLKINV_5264
    );
  Slave_nstate_FFd4_In54_SW0 : X_LUT4
    generic map(
      INIT => X"7F73",
      LOC => "SLICE_X16Y38"
    )
    port map (
      ADR0 => N68_0,
      ADR1 => Slave_nstate_FFd3_1642,
      ADR2 => Slave_pstate_cmp_eq0002_0,
      ADR3 => Slave_N38_0,
      O => Slave_nstate_FFd4_In54_SW0_O_pack_1
    );
  Slave_nstate_cmp_eq0000_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_cmp_eq0000_5306,
      O => Slave_nstate_cmp_eq0000_0
    );
  Slave_nstate_cmp_eq0000_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_cmp_eq0000_SW0_O_pack_1,
      O => Slave_nstate_cmp_eq0000_SW0_O
    );
  Slave_nstate_cmp_eq0000_SW0 : X_LUT4
    generic map(
      INIT => X"FFEF",
      LOC => "SLICE_X18Y38"
    )
    port map (
      ADR0 => Slave_i2cAddr(3),
      ADR1 => Slave_i2cAddr(1),
      ADR2 => Slave_i2cAddr(7),
      ADR3 => Slave_i2cAddr(2),
      O => Slave_nstate_cmp_eq0000_SW0_O_pack_1
    );
  Slave_delay_count_mux0000_0_111_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000_0_111_5330,
      O => Slave_delay_count_mux0000_0_111_0
    );
  Slave_delay_count_mux0000_0_111_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg_cmp_eq00001_SW1_O_pack_1,
      O => Slave_shiftReg_cmp_eq00001_SW1_O
    );
  Slave_shiftReg_cmp_eq00001_SW1 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X18Y22"
    )
    port map (
      ADR0 => Slave_delay_count(6),
      ADR1 => Slave_delay_count(13),
      ADR2 => Slave_delay_count(1),
      ADR3 => Slave_delay_count(5),
      O => Slave_shiftReg_cmp_eq00001_SW1_O_pack_1
    );
  Slave_nstate_FFd4_In29_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd4_In29,
      O => Slave_nstate_FFd4_In29_0
    );
  Slave_nstate_FFd4_In29_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd1_In1311_SW0_O_pack_1,
      O => Slave_pstate_FFd1_In1311_SW0_O
    );
  Slave_pstate_FFd1_In1311_SW0 : X_LUT4
    generic map(
      INIT => X"FAFF",
      LOC => "SLICE_X15Y34"
    )
    port map (
      ADR0 => Slave_counter(0),
      ADR1 => VCC,
      ADR2 => Slave_counter(2),
      ADR3 => Slave_counter(1),
      O => Slave_pstate_FFd1_In1311_SW0_O_pack_1
    );
  Slave_Dir_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Dir_mux0000160,
      O => Slave_Dir_DXMUX_5385
    );
  Slave_Dir_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Dir_mux000090_O_pack_1,
      O => Slave_Dir_mux000090_O
    );
  Slave_Dir_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Dir_mux000051_4931,
      O => Slave_Dir_SRINV_5370
    );
  Slave_Dir_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_Dir_CLKINV_5369
    );
  Slave_counter_mux0000_5_13_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_mux0000_5_13_5411,
      O => Slave_counter_mux0000_5_13_0
    );
  Slave_counter_mux0000_5_13_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_mux0000_5_13_SW0_O_pack_1,
      O => Slave_counter_mux0000_5_13_SW0_O
    );
  Slave_counter_mux0000_5_13_SW0 : X_LUT4
    generic map(
      INIT => X"FF5F",
      LOC => "SLICE_X16Y32"
    )
    port map (
      ADR0 => Slave_ClkRisingEdge_1699,
      ADR1 => VCC,
      ADR2 => Slave_nstate_FFd3_1642,
      ADR3 => Slave_counter(0),
      O => Slave_counter_mux0000_5_13_SW0_O_pack_1
    );
  Slave_counter_mux0000_4_37_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_mux0000_4_23_O_pack_1,
      O => Slave_counter_mux0000_4_23_O
    );
  Slave_counter_mux0000_4_23 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X14Y34"
    )
    port map (
      ADR0 => Slave_counter(3),
      ADR1 => Slave_counter_mux0000_4_17_0,
      ADR2 => Slave_nstate_FFd1_1598,
      ADR3 => Slave_counter(4),
      O => Slave_counter_mux0000_4_23_O_pack_1
    );
  Slave_in_i2c_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X21Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_in_i2c_mux000070,
      O => Slave_in_i2c_DXMUX_5466
    );
  Slave_in_i2c_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_in_i2c_mux000034_O_pack_1,
      O => Slave_in_i2c_mux000034_O
    );
  Slave_in_i2c_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X21Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_in_i2c_mux000068_2763,
      O => Slave_in_i2c_SRINV_5451
    );
  Slave_in_i2c_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X21Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_in_i2c_CLKINV_5450
    );
  Slave_N36_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N36,
      O => Slave_N36_0
    );
  Slave_N36_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => N46_pack_1,
      O => N46
    );
  Slave_shiftReg_cmp_eq00001_SW0 : X_LUT4
    generic map(
      INIT => X"FFFA",
      LOC => "SLICE_X18Y23"
    )
    port map (
      ADR0 => Slave_delay_count(14),
      ADR1 => VCC,
      ADR2 => Slave_delay_count(12),
      ADR3 => Slave_delay_count(15),
      O => N46_pack_1
    );
  Slave_ridvalid_mux00000_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_cmp_eq0009_pack_1,
      O => Slave_pstate_cmp_eq0009
    );
  Slave_pstate_cmp_eq00091 : X_LUT4
    generic map(
      INIT => X"2020",
      LOC => "SLICE_X17Y33"
    )
    port map (
      ADR0 => Slave_counter_and0000,
      ADR1 => Slave_counter(3),
      ADR2 => Slave_counter(0),
      ADR3 => VCC,
      O => Slave_pstate_cmp_eq0009_pack_1
    );
  N99_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => N99,
      O => N99_0
    );
  N99_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd2_In121_pack_1,
      O => Slave_pstate_FFd2_In121_1647
    );
  Slave_pstate_FFd2_In121 : X_LUT4
    generic map(
      INIT => X"FFF8",
      LOC => "SLICE_X15Y41"
    )
    port map (
      ADR0 => Slave_N31_0,
      ADR1 => Slave_nstate_FFd4_1597,
      ADR2 => Slave_nstate_FFd1_1598,
      ADR3 => Slave_nstate_FFd2_1691,
      O => Slave_pstate_FFd2_In121_pack_1
    );
  Slave_pstate_FFd1_In15_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd1_In15_SW0_O_pack_1,
      O => Slave_pstate_FFd1_In15_SW0_O
    );
  Slave_pstate_FFd1_In15_SW0 : X_LUT4
    generic map(
      INIT => X"C888",
      LOC => "SLICE_X14Y39"
    )
    port map (
      ADR0 => Slave_pstate_FFd1_1706,
      ADR1 => Slave_doutvalid_mux00001_0,
      ADR2 => OEM_I2C_Clk_IBUF_1604,
      ADR3 => Slave_DataRisingEdge_1595,
      O => Slave_pstate_FFd1_In15_SW0_O_pack_1
    );
  Slave_nstate_FFd3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X15Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd3_In55,
      O => Slave_nstate_FFd3_DXMUX_5595
    );
  Slave_nstate_FFd3_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd3_In24_O_pack_1,
      O => Slave_nstate_FFd3_In24_O
    );
  Slave_nstate_FFd3_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_nstate_FFd3_In41_5249,
      O => Slave_nstate_FFd3_SRINV_5580
    );
  Slave_nstate_FFd3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_nstate_FFd3_CLKINV_5579
    );
  N105_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => N105,
      O => N105_0
    );
  N105_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_and0000_pack_1,
      O => Slave_counter_and0000
    );
  Slave_pstate_cmp_eq000311 : X_LUT4
    generic map(
      INIT => X"0100",
      LOC => "SLICE_X16Y34"
    )
    port map (
      ADR0 => Slave_counter(1),
      ADR1 => Slave_counter(2),
      ADR2 => Slave_counter(5),
      ADR3 => Slave_counter(4),
      O => Slave_counter_and0000_pack_1
    );
  N50_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000_0_31_O_pack_1,
      O => Slave_delay_count_mux0000_0_31_O
    );
  Slave_delay_count_mux0000_0_31 : X_LUT4
    generic map(
      INIT => X"0080",
      LOC => "SLICE_X20Y24"
    )
    port map (
      ADR0 => Slave_delay_count_cmp_eq0000_0,
      ADR1 => Slave_N36_0,
      ADR2 => Slave_nstate_FFd2_1691,
      ADR3 => Slave_delay_count(5),
      O => Slave_delay_count_mux0000_0_31_O_pack_1
    );
  Slave_ack_count_0_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X22Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_mux0000(0),
      O => Slave_ack_count_0_DXMUX_5674
    );
  Slave_ack_count_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_mux0000_0_SW1_O_pack_1,
      O => Slave_ack_count_mux0000_0_SW1_O
    );
  Slave_ack_count_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_ack_count_0_CLKINV_5659
    );
  Slave_ack_count_mux0000_0_SW1 : X_LUT4
    generic map(
      INIT => X"EEEA",
      LOC => "SLICE_X22Y30"
    )
    port map (
      ADR0 => Slave_nstate_FFd4_1597,
      ADR1 => Slave_nstate_FFd1_1598,
      ADR2 => Slave_ack_count_addsub0000(0),
      ADR3 => Slave_ack_count_cmp_eq0000_1679,
      O => Slave_ack_count_mux0000_0_SW1_O_pack_1
    );
  Slave_pstate_FFd2_In192_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd2_In192_5699,
      O => Slave_pstate_FFd2_In192_0
    );
  Slave_pstate_FFd2_In192_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_pstate_FFd2_In159_O_pack_1,
      O => Slave_pstate_FFd2_In159_O
    );
  Slave_pstate_FFd2_In159 : X_LUT4
    generic map(
      INIT => X"EEF5",
      LOC => "SLICE_X14Y32"
    )
    port map (
      ADR0 => Slave_counter(4),
      ADR1 => N86,
      ADR2 => N85_0,
      ADR3 => Slave_counter(5),
      O => Slave_pstate_FFd2_In159_O_pack_1
    );
  Slave_shiftReg_6_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg_mux0001_6_1_5727,
      O => Slave_shiftReg_6_DXMUX_5730
    );
  Slave_shiftReg_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => N145_pack_1,
      O => N145
    );
  Slave_shiftReg_6_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => N30,
      O => Slave_shiftReg_6_SRINV_5715
    );
  Slave_shiftReg_6_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_shiftReg_6_CLKINV_5714
    );
  Slave_counter_5_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X15Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_mux0000_0_Q_5758,
      O => Slave_counter_5_DXMUX_5761
    );
  Slave_counter_5_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_mux0000_0_SW3_O_pack_1,
      O => Slave_counter_mux0000_0_SW3_O
    );
  Slave_counter_5_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_counter_5_CLKINV_5746
    );
  Slave_counter_mux0000_0_SW3 : X_LUT4
    generic map(
      INIT => X"BAFA",
      LOC => "SLICE_X15Y28"
    )
    port map (
      ADR0 => Slave_nstate_FFd2_1691,
      ADR1 => Slave_counter(4),
      ADR2 => Slave_nstate_FFd3_1642,
      ADR3 => Slave_Madd_counter_addsub0000_cy(3),
      O => Slave_counter_mux0000_0_SW3_O_pack_1
    );
  Slave_Dir_and0000_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Dir_and0000,
      O => Slave_Dir_and0000_0
    );
  Slave_Dir_and0000_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => N48_pack_1,
      O => N48
    );
  Slave_ack_count_cmp_eq00001_SW0 : X_LUT4
    generic map(
      INIT => X"FEFE",
      LOC => "SLICE_X22Y34"
    )
    port map (
      ADR0 => Slave_ack_count(3),
      ADR1 => Slave_ack_count(11),
      ADR2 => Slave_ack_count(10),
      ADR3 => VCC,
      O => N48_pack_1
    );
  Slave_shiftReg_7_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X21Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg_mux0001(7),
      O => Slave_shiftReg_7_DXMUX_5815
    );
  Slave_shiftReg_7_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_shiftReg_mux0001_7_1_SW0_O_pack_1,
      O => Slave_shiftReg_mux0001_7_1_SW0_O
    );
  Slave_shiftReg_7_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X21Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_shiftReg_7_CLKINV_5800
    );
  Slave_shiftReg_mux0001_7_1_SW0 : X_LUT4
    generic map(
      INIT => X"FF40",
      LOC => "SLICE_X21Y39"
    )
    port map (
      ADR0 => Slave_delay_count(5),
      ADR1 => Slave_delay_count_cmp_eq0000_0,
      ADR2 => Slave_N36_0,
      ADR3 => Slave_ClkFallingEdge_1671,
      O => Slave_shiftReg_mux0001_7_1_SW0_O_pack_1
    );
  Slave_counter_3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X15Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_counter_mux0000_2_Q_5842,
      O => Slave_counter_3_DXMUX_5845
    );
  Slave_counter_3_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N241_pack_1,
      O => Slave_N241
    );
  Slave_counter_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_counter_3_CLKINV_5828
    );
  Slave_counter_mux0000_0_111 : X_LUT4
    generic map(
      INIT => X"FFCC",
      LOC => "SLICE_X15Y33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_N18_0,
      ADR2 => VCC,
      ADR3 => Slave_nstate_FFd2_1691,
      O => Slave_N241_pack_1
    );
  Slave_ridvalid_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ridvalid_mux000037,
      O => Slave_ridvalid_DXMUX_5877
    );
  Slave_ridvalid_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ridvalid_mux000014_O_pack_1,
      O => Slave_ridvalid_mux000014_O
    );
  Slave_ridvalid_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ridvalid_mux00000_5516,
      O => Slave_ridvalid_SRINV_5862
    );
  Slave_ridvalid_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_ridvalid_CLKINV_5861
    );
  Slave_nstate_FFd4_In19_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_N311_pack_1,
      O => Slave_N311
    );
  Slave_nstate_FFd4_In31 : X_LUT4
    generic map(
      INIT => X"FF22",
      LOC => "SLICE_X17Y38"
    )
    port map (
      ADR0 => Slave_nstate_FFd7_1710,
      ADR1 => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1,
      ADR2 => VCC,
      ADR3 => Slave_nstate_FFd6_1709,
      O => Slave_N311_pack_1
    );
  Slave_ClkRisingEdge_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X18Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ClkRisingEdge_and00001,
      O => Slave_ClkRisingEdge_DYMUX_5922
    );
  Slave_ClkRisingEdge_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X18Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_prevClk_1667,
      O => Slave_ClkRisingEdge_SRINV_5912
    );
  Slave_ClkRisingEdge_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X18Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_ClkRisingEdge_CLKINV_5911
    );
  Slave_delay_count_11_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(11),
      O => Slave_delay_count_11_DXMUX_5957
    );
  Slave_delay_count_11_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(10),
      O => Slave_delay_count_11_DYMUX_5946
    );
  Slave_delay_count_11_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_delay_count_11_CLKINV_5938
    );
  Slave_delay_count_mux0000_10_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X20Y22"
    )
    port map (
      ADR0 => Slave_delay_count(10),
      ADR1 => Slave_delay_count_or0000_1625,
      ADR2 => Slave_delay_count_share0000(10),
      ADR3 => Slave_N3,
      O => Slave_delay_count_mux0000(10)
    );
  Slave_delay_count_13_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(13),
      O => Slave_delay_count_13_DXMUX_5991
    );
  Slave_delay_count_13_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(12),
      O => Slave_delay_count_13_DYMUX_5980
    );
  Slave_delay_count_13_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_delay_count_13_CLKINV_5972
    );
  Slave_delay_count_mux0000_12_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X20Y23"
    )
    port map (
      ADR0 => Slave_delay_count(12),
      ADR1 => Slave_N17_0,
      ADR2 => Slave_N3,
      ADR3 => Slave_delay_count_share0000(12),
      O => Slave_delay_count_mux0000(12)
    );
  Slave_delay_count_15_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(15),
      O => Slave_delay_count_15_DXMUX_6025
    );
  Slave_delay_count_15_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_delay_count_mux0000(14),
      O => Slave_delay_count_15_DYMUX_6014
    );
  Slave_delay_count_15_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_delay_count_15_CLKINV_6006
    );
  Slave_delay_count_mux0000_14_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X20Y25"
    )
    port map (
      ADR0 => Slave_delay_count(14),
      ADR1 => Slave_N17_0,
      ADR2 => Slave_delay_count_share0000(14),
      ADR3 => Slave_N3,
      O => Slave_delay_count_mux0000(14)
    );
  Slave_ack_count_11_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_mux0000(11),
      O => Slave_ack_count_11_DXMUX_6059
    );
  Slave_ack_count_11_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_mux0000(10),
      O => Slave_ack_count_11_DYMUX_6048
    );
  Slave_ack_count_11_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_ack_count_11_CLKINV_6040
    );
  Slave_ack_count_mux0000_10_2 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X24Y34"
    )
    port map (
      ADR0 => Slave_N0,
      ADR1 => Slave_N40_0,
      ADR2 => Slave_ack_count(10),
      ADR3 => Slave_ack_count_addsub0000(10),
      O => Slave_ack_count_mux0000(10)
    );
  Slave_ack_count_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_mux0000(1),
      O => Slave_ack_count_1_DYMUX_6077
    );
  Slave_ack_count_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_ack_count_1_CLKINV_6069
    );
  Slave_ack_count_mux0000_1_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X24Y31"
    )
    port map (
      ADR0 => Slave_ack_count(1),
      ADR1 => Slave_ack_count_addsub0000(1),
      ADR2 => Slave_N40_0,
      ADR3 => Slave_N0,
      O => Slave_ack_count_mux0000(1)
    );
  Slave_ack_count_3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_mux0000(3),
      O => Slave_ack_count_3_DXMUX_6111
    );
  Slave_ack_count_3_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_mux0000(2),
      O => Slave_ack_count_3_DYMUX_6100
    );
  Slave_ack_count_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_ack_count_3_CLKINV_6092
    );
  Slave_ack_count_mux0000_2_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X24Y30"
    )
    port map (
      ADR0 => Slave_ack_count(2),
      ADR1 => Slave_N0,
      ADR2 => Slave_N40_0,
      ADR3 => Slave_ack_count_addsub0000(2),
      O => Slave_ack_count_mux0000(2)
    );
  Slave_ack_count_5_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_mux0000(5),
      O => Slave_ack_count_5_DXMUX_6145
    );
  Slave_ack_count_5_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_mux0000(4),
      O => Slave_ack_count_5_DYMUX_6134
    );
  Slave_ack_count_5_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_ack_count_5_CLKINV_6126
    );
  Slave_ack_count_mux0000_4_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X24Y33"
    )
    port map (
      ADR0 => Slave_N0,
      ADR1 => Slave_ack_count(4),
      ADR2 => Slave_ack_count_addsub0000(4),
      ADR3 => Slave_N40_0,
      O => Slave_ack_count_mux0000(4)
    );
  Slave_ack_count_7_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_mux0000(7),
      O => Slave_ack_count_7_DXMUX_6179
    );
  Slave_ack_count_7_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ack_count_mux0000(6),
      O => Slave_ack_count_7_DYMUX_6168
    );
  Slave_ack_count_7_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => Clk_100MHz_BUFGP,
      O => Slave_ack_count_7_CLKINV_6160
    );
  Slave_ack_count_mux0000_6_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X24Y32"
    )
    port map (
      ADR0 => Slave_ack_count(6),
      ADR1 => Slave_N0,
      ADR2 => Slave_N40_0,
      ADR3 => Slave_ack_count_addsub0000(6),
      O => Slave_ack_count_mux0000(6)
    );
  Slave_ack_count_11_rt : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X25Y35"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Slave_ack_count(11),
      ADR3 => VCC,
      O => Slave_ack_count_11_rt_3937
    );
  Slave_pstate_FFd2_In26_F : X_LUT4
    generic map(
      INIT => X"EEFE",
      LOC => "SLICE_X16Y37"
    )
    port map (
      ADR0 => Slave_nstate_FFd6_1709,
      ADR1 => Slave_nstate_FFd5_1646,
      ADR2 => Slave_nstate_FFd2_1691,
      ADR3 => Slave_Mcompar_pstate_cmp_gt0000_cy_5_Q,
      O => N182
    );
  Slave_pstate_FFd3_In103_F : X_LUT4
    generic map(
      INIT => X"FAEE",
      LOC => "SLICE_X14Y37"
    )
    port map (
      ADR0 => Slave_pstate_FFd3_In28_0,
      ADR1 => N161_0,
      ADR2 => N162_0,
      ADR3 => Slave_pstate_cmp_eq0002_0,
      O => N186
    );
  Slave_shiftReg_mux0001_0_122_SW1_F : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X18Y37"
    )
    port map (
      ADR0 => Slave_N39,
      ADR1 => Slave_nstate_FFd4_1597,
      ADR2 => Slave_shiftReg(7),
      ADR3 => Slave_shiftReg(6),
      O => N163
    );
  Slave_delay_count_mux0000_0_182_F : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X19Y20"
    )
    port map (
      ADR0 => Slave_delay_count(4),
      ADR1 => Slave_delay_count(2),
      ADR2 => Slave_delay_count(7),
      ADR3 => Slave_delay_count_mux0000_0_162_0,
      O => N184
    );
  Slave_DataRisingEdge_and000111 : X_LUT4
    generic map(
      INIT => X"8888",
      LOC => "SLICE_X15Y45"
    )
    port map (
      ADR0 => Slave_edge(1),
      ADR1 => Slave_edge(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_DataRisingEdge_and00011
    );
  Slave_shiftReg_mux0001_1_1 : X_LUT4
    generic map(
      INIT => X"CCC8",
      LOC => "SLICE_X16Y40"
    )
    port map (
      ADR0 => Slave_nstate_FFd4_1597,
      ADR1 => Slave_shiftReg(1),
      ADR2 => Slave_N18_0,
      ADR3 => N145,
      O => Slave_shiftReg_mux0001_1_1_1984
    );
  Slave_shiftReg_mux0001_2_1 : X_LUT4
    generic map(
      INIT => X"CCC8",
      LOC => "SLICE_X17Y41"
    )
    port map (
      ADR0 => Slave_N18_0,
      ADR1 => Slave_shiftReg(2),
      ADR2 => N145,
      ADR3 => Slave_nstate_FFd4_1597,
      O => Slave_shiftReg_mux0001_2_1_2035
    );
  Slave_shiftReg_mux0001_3_1 : X_LUT4
    generic map(
      INIT => X"FE00",
      LOC => "SLICE_X18Y40"
    )
    port map (
      ADR0 => Slave_nstate_FFd4_1597,
      ADR1 => N145,
      ADR2 => Slave_N18_0,
      ADR3 => Slave_shiftReg(3),
      O => Slave_shiftReg_mux0001_3_1_2069
    );
  Slave_shiftReg_mux0001_4_1 : X_LUT4
    generic map(
      INIT => X"FE00",
      LOC => "SLICE_X19Y40"
    )
    port map (
      ADR0 => Slave_nstate_FFd4_1597,
      ADR1 => Slave_N18_0,
      ADR2 => N145,
      ADR3 => Slave_shiftReg(4),
      O => Slave_shiftReg_mux0001_4_1_2102
    );
  Slave_shiftReg_mux0001_5_1 : X_LUT4
    generic map(
      INIT => X"F0E0",
      LOC => "SLICE_X19Y41"
    )
    port map (
      ADR0 => N145,
      ADR1 => Slave_N18_0,
      ADR2 => Slave_shiftReg(5),
      ADR3 => Slave_nstate_FFd4_1597,
      O => Slave_shiftReg_mux0001_5_1_2135
    );
  Slave_delay_count_15_rt : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X21Y24"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Slave_delay_count(15),
      O => Slave_delay_count_15_rt_3566
    );
  Slave_Mcompar_pstate_cmp_gt0000_lut_1_1 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X19Y21"
    )
    port map (
      ADR0 => Slave_delay_count(8),
      ADR1 => Slave_delay_count(6),
      ADR2 => Slave_delay_count(5),
      ADR3 => Slave_delay_count(7),
      O => Slave_Mcompar_pstate_cmp_gt0000_lut_1_1_3592
    );
  Slave_Mcompar_pstate_cmp_gt0000_lut_3_1 : X_LUT4
    generic map(
      INIT => X"0003",
      LOC => "SLICE_X19Y22"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_delay_count(15),
      ADR2 => Slave_delay_count(13),
      ADR3 => Slave_delay_count(14),
      O => Slave_Mcompar_pstate_cmp_gt0000_lut_3_1_3624
    );
  Slave_Mcompar_pstate_cmp_gt0000_lut_1_Q : X_LUT4
    generic map(
      INIT => X"8080",
      LOC => "SLICE_X19Y23"
    )
    port map (
      ADR0 => Slave_delay_count(2),
      ADR1 => Slave_delay_count(3),
      ADR2 => Slave_delay_count(4),
      ADR3 => VCC,
      O => Slave_Mcompar_pstate_cmp_gt0000_lut_1_Q_3652
    );
  Slave_Mcompar_pstate_cmp_gt0000_lut_3_Q : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X19Y24"
    )
    port map (
      ADR0 => Slave_delay_count(10),
      ADR1 => Slave_delay_count(8),
      ADR2 => Slave_delay_count(7),
      ADR3 => Slave_delay_count(9),
      O => Slave_Mcompar_pstate_cmp_gt0000_lut_3_Q_3683
    );
  Slave_Mcompar_pstate_cmp_gt0000_lut_5_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X19Y25"
    )
    port map (
      ADR0 => Slave_delay_count(12),
      ADR1 => Slave_delay_count(14),
      ADR2 => Slave_delay_count(15),
      ADR3 => Slave_delay_count(13),
      O => Slave_Mcompar_pstate_cmp_gt0000_lut_5_Q_3713
    );
  Slave_in_i2c_mux000034 : X_LUT4
    generic map(
      INIT => X"FE00",
      LOC => "SLICE_X21Y34"
    )
    port map (
      ADR0 => Slave_N261_0,
      ADR1 => Slave_in_i2c_mux000022_0,
      ADR2 => Slave_in_i2c_mux000010_0,
      ADR3 => Slave_nstate_FFd1_1598,
      O => Slave_in_i2c_mux000034_O_pack_1
    );
  Slave_nstate_FFd3_In24 : X_LUT4
    generic map(
      INIT => X"A8FD",
      LOC => "SLICE_X15Y38"
    )
    port map (
      ADR0 => Slave_pstate_cmp_eq0002_0,
      ADR1 => Slave_pstate_FFd2_1641,
      ADR2 => Slave_pstate_FFd3_1644,
      ADR3 => Slave_N38_0,
      O => Slave_nstate_FFd3_In24_O_pack_1
    );
  Slave_shiftReg_mux0001_6_1_SW0 : X_LUT4
    generic map(
      INIT => X"AA2A",
      LOC => "SLICE_X20Y38"
    )
    port map (
      ADR0 => Slave_in_i2c_mux00002_0,
      ADR1 => Slave_N36_0,
      ADR2 => Slave_delay_count_cmp_eq0000_0,
      ADR3 => Slave_delay_count(5),
      O => N145_pack_1
    );
  Slave_ridvalid_mux000014 : X_LUT4
    generic map(
      INIT => X"AAA8",
      LOC => "SLICE_X16Y28"
    )
    port map (
      ADR0 => N169_0,
      ADR1 => Slave_N28_0,
      ADR2 => Slave_nstate_FFd3_1642,
      ADR3 => Slave_nstate_FFd1_1598,
      O => Slave_ridvalid_mux000014_O_pack_1
    );
  Slave_ClkRisingEdge_and000011 : X_LUT4
    generic map(
      INIT => X"F000",
      LOC => "SLICE_X18Y36"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Slave_ClkEdge(0),
      ADR3 => Slave_ClkEdge(1),
      O => Slave_ClkRisingEdge_and00001
    );
  Slave_DataRisingEdge : X_SFF
    generic map(
      LOC => "SLICE_X15Y45",
      INIT => '0'
    )
    port map (
      I => Slave_DataRisingEdge_DYMUX_1921,
      CE => VCC,
      CLK => Slave_DataRisingEdge_CLKINV_1910,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => Slave_DataRisingEdge_SRINV_1911,
      O => Slave_DataRisingEdge_1595
    );
  Slave_shiftReg_mux0001_0_122_SW1_G : X_LUT4
    generic map(
      INIT => X"EAAA",
      LOC => "SLICE_X18Y37"
    )
    port map (
      ADR0 => Slave_shiftReg(7),
      ADR1 => Slave_ClkRisingEdge_1699,
      ADR2 => Slave_nstate_FFd3_1642,
      ADR3 => Slave_shiftReg(6),
      O => N164
    );
  Slave_delay_count_mux0000_0_182_G : X_LUT4
    generic map(
      INIT => X"FF7F",
      LOC => "SLICE_X19Y20"
    )
    port map (
      ADR0 => Slave_delay_count(0),
      ADR1 => Slave_delay_count(2),
      ADR2 => Slave_delay_count(8),
      ADR3 => Slave_delay_count_mux0000_0_124_0,
      O => N185
    );
  Slave_counter_mux0000_1_G : X_LUT4
    generic map(
      INIT => X"FCAC",
      LOC => "SLICE_X14Y28"
    )
    port map (
      ADR0 => Slave_N18_0,
      ADR1 => Slave_N39,
      ADR2 => Slave_counter(4),
      ADR3 => Slave_nstate_FFd2_1691,
      O => N166
    );
  Slave_doutvalid_mux0000211 : X_LUT4
    generic map(
      INIT => X"AAA8",
      LOC => "SLICE_X16Y26"
    )
    port map (
      ADR0 => N169_0,
      ADR1 => Slave_doutvalid_mux00006_0,
      ADR2 => Slave_nstate_FFd7_1710,
      ADR3 => Slave_nstate_FFd2_1691,
      O => Slave_doutvalid_mux0000211_O_pack_1
    );
  Slave_counter_mux0000_5_29 : X_LUT4
    generic map(
      INIT => X"7350",
      LOC => "SLICE_X16Y31"
    )
    port map (
      ADR0 => Slave_ClkRisingEdge_1699,
      ADR1 => Slave_counter_and0000,
      ADR2 => Slave_nstate_FFd3_1642,
      ADR3 => Slave_nstate_FFd1_1598,
      O => Slave_counter_mux0000_5_29_O_pack_1
    );
  Slave_pstate_FFd2_In91 : X_LUT4
    generic map(
      INIT => X"0A08",
      LOC => "SLICE_X14Y36"
    )
    port map (
      ADR0 => Slave_pstate_cmp_eq0008_0,
      ADR1 => Slave_pstate_FFd2_In65_0,
      ADR2 => N74_0,
      ADR3 => Slave_N391_0,
      O => Slave_pstate_FFd2_In91_O_pack_1
    );
  Slave_pstate_FFd1_In26 : X_LUT4
    generic map(
      INIT => X"C400",
      LOC => "SLICE_X14Y38"
    )
    port map (
      ADR0 => Slave_N38_0,
      ADR1 => Slave_ridvalid_mux00008_0,
      ADR2 => Slave_pstate_cmp_eq0002_0,
      ADR3 => Slave_nstate_FFd3_1642,
      O => Slave_pstate_FFd1_In26_O_pack_1
    );
  Slave_pstate_FFd1_In1313 : X_LUT4
    generic map(
      INIT => X"80CC",
      LOC => "SLICE_X15Y37"
    )
    port map (
      ADR0 => Slave_N401_0,
      ADR1 => Slave_nstate_FFd1_In9_0,
      ADR2 => Slave_nstate_FFd4_In29_0,
      ADR3 => Slave_pstate_cmp_eq0008_0,
      O => Slave_pstate_FFd1_In1313_pack_1
    );
  Slave_nstate_FFd1_In8 : X_LUT4
    generic map(
      INIT => X"A2FF",
      LOC => "SLICE_X15Y36"
    )
    port map (
      ADR0 => Slave_N401_0,
      ADR1 => Slave_N391_0,
      ADR2 => Slave_counter(2),
      ADR3 => Slave_pstate_cmp_eq0008_0,
      O => Slave_nstate_FFd1_In8_O_pack_1
    );
  Slave_Dir_mux000090 : X_LUT4
    generic map(
      INIT => X"FFFB",
      LOC => "SLICE_X20Y27"
    )
    port map (
      ADR0 => Slave_Dir_mux000080_0,
      ADR1 => Slave_N36_0,
      ADR2 => Slave_Dir_mux000064_0,
      ADR3 => Slave_Dir_mux000069_0,
      O => Slave_Dir_mux000090_O_pack_1
    );
  Slave_pstate_FFd2_In26_G : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X16Y37"
    )
    port map (
      ADR0 => Slave_nstate_FFd6_1709,
      ADR1 => Slave_nstate_FFd1_1598,
      ADR2 => Slave_nstate_FFd2_1691,
      ADR3 => Slave_nstate_FFd5_1646,
      O => N183
    );
  Slave_Mcompar_pstate_cmp_gt0000_lut_0_1_INV_0 : X_LUT4
    generic map(
      INIT => X"5555",
      LOC => "SLICE_X19Y21"
    )
    port map (
      ADR0 => Slave_delay_count(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_Mcompar_pstate_cmp_gt0000_lut_0_1
    );
  Slave_nstate_FFd5_In11 : X_LUT4
    generic map(
      INIT => X"2200",
      LOC => "SLICE_X16Y39"
    )
    port map (
      ADR0 => Slave_nstate_FFd3_1642,
      ADR1 => Slave_pstate_FFd3_1644,
      ADR2 => VCC,
      ADR3 => Slave_pstate_cmp_eq0002_0,
      O => Slave_nstate_FFd5_In1
    );
  Slave_pstate_cmp_eq0010 : X_LUT4
    generic map(
      INIT => X"0200",
      LOC => "SLICE_X16Y33"
    )
    port map (
      ADR0 => Slave_counter(1),
      ADR1 => N52,
      ADR2 => Slave_counter(5),
      ADR3 => Slave_counter(4),
      O => Slave_pstate_cmp_eq0010_3025
    );
  Slave_DataFallingEdge_not00011 : X_LUT4
    generic map(
      INIT => X"EEFF",
      LOC => "SLICE_X15Y45"
    )
    port map (
      ADR0 => Slave_edge(1),
      ADR1 => Slave_edge(0),
      ADR2 => VCC,
      ADR3 => Slave_prevData_1591,
      O => Slave_DataFallingEdge_not0001
    );
  Slave_shiftReg_0 : X_SFF
    generic map(
      LOC => "SLICE_X16Y41",
      INIT => '0'
    )
    port map (
      I => Slave_shiftReg_0_DYMUX_1953,
      CE => VCC,
      CLK => Slave_shiftReg_0_CLKINV_1944,
      SET => GND,
      RST => GND,
      SSET => Slave_shiftReg_0_SRINV_1945,
      SRST => GND,
      O => Slave_shiftReg(0)
    );
  Slave_delay_count_or0000_SW0 : X_LUT4
    generic map(
      INIT => X"EEEE",
      LOC => "SLICE_X16Y41"
    )
    port map (
      ADR0 => Slave_nstate_FFd4_1597,
      ADR1 => Slave_nstate_FFd1_1598,
      ADR2 => VCC,
      ADR3 => VCC,
      O => N2
    );
  Slave_shiftReg_1 : X_SFF
    generic map(
      LOC => "SLICE_X16Y40",
      INIT => '0'
    )
    port map (
      I => Slave_shiftReg_1_DYMUX_1987,
      CE => VCC,
      CLK => Slave_shiftReg_1_CLKINV_1978,
      SET => GND,
      RST => GND,
      SSET => Slave_shiftReg_1_SRINV_1979,
      SRST => GND,
      O => Slave_shiftReg(1)
    );
  Slave_nstate_FFd4_In6 : X_LUT4
    generic map(
      INIT => X"0AAA",
      LOC => "SLICE_X16Y40"
    )
    port map (
      ADR0 => Slave_nstate_FFd4_1597,
      ADR1 => VCC,
      ADR2 => Slave_DataFallingEdge_1605,
      ADR3 => OEM_I2C_Clk_IBUF_1604,
      O => Slave_nstate_FFd4_In6_1997
    );
  Slave_prevData : X_FF
    generic map(
      LOC => "SLICE_X14Y45",
      INIT => '0'
    )
    port map (
      I => Slave_prevData_DYMUX_2014,
      CE => VCC,
      CLK => Slave_prevData_CLKINV_2005,
      SET => GND,
      RST => GND,
      O => Slave_prevData_1591
    );
  Slave_shiftReg_2 : X_SFF
    generic map(
      LOC => "SLICE_X17Y41",
      INIT => '0'
    )
    port map (
      I => Slave_shiftReg_2_DYMUX_2038,
      CE => VCC,
      CLK => Slave_shiftReg_2_CLKINV_2029,
      SET => GND,
      RST => GND,
      SSET => Slave_shiftReg_2_SRINV_2030,
      SRST => GND,
      O => Slave_shiftReg(2)
    );
  Slave_nstate_FFd3_In38 : X_LUT4
    generic map(
      INIT => X"8800",
      LOC => "SLICE_X17Y41"
    )
    port map (
      ADR0 => OEM_I2C_Clk_IBUF_1604,
      ADR1 => Slave_DataFallingEdge_1605,
      ADR2 => VCC,
      ADR3 => Slave_nstate_FFd4_1597,
      O => Slave_nstate_FFd3_In38_2048
    );
  Slave_shiftReg_3 : X_SFF
    generic map(
      LOC => "SLICE_X18Y40",
      INIT => '0'
    )
    port map (
      I => Slave_shiftReg_3_DYMUX_2072,
      CE => VCC,
      CLK => Slave_shiftReg_3_CLKINV_2063,
      SET => GND,
      RST => GND,
      SSET => Slave_shiftReg_3_SRINV_2064,
      SRST => GND,
      O => Slave_shiftReg(3)
    );
  Slave_pstate_FFd1_In1316_SW0 : X_LUT4
    generic map(
      INIT => X"04CC",
      LOC => "SLICE_X18Y40"
    )
    port map (
      ADR0 => Slave_DataFallingEdge_1605,
      ADR1 => Slave_nstate_FFd4_1597,
      ADR2 => Slave_DataRisingEdge_1595,
      ADR3 => OEM_I2C_Clk_IBUF_1604,
      O => N70
    );
  Slave_shiftReg_4 : X_SFF
    generic map(
      LOC => "SLICE_X19Y40",
      INIT => '0'
    )
    port map (
      I => Slave_shiftReg_4_DYMUX_2105,
      CE => VCC,
      CLK => Slave_shiftReg_4_CLKINV_2096,
      SET => GND,
      RST => GND,
      SSET => Slave_shiftReg_4_SRINV_2097,
      SRST => GND,
      O => Slave_shiftReg(4)
    );
  Slave_ack_count_cmp_eq00001_SW1 : X_LUT4
    generic map(
      INIT => X"FFFB",
      LOC => "SLICE_X23Y35"
    )
    port map (
      ADR0 => Slave_ack_count(4),
      ADR1 => Slave_ack_count(2),
      ADR2 => Slave_ack_count(7),
      ADR3 => Slave_ack_count(9),
      O => N76
    );
  Slave_i2cAddr_1 : X_FF
    generic map(
      LOC => "SLICE_X18Y41",
      INIT => '0'
    )
    port map (
      I => Slave_i2cAddr_2_DYMUX_2508,
      CE => Slave_i2cAddr_2_CEINV_2505,
      CLK => Slave_i2cAddr_2_CLKINV_2506,
      SET => GND,
      RST => GND,
      O => Slave_i2cAddr(1)
    );
  Slave_i2cAddr_2 : X_FF
    generic map(
      LOC => "SLICE_X18Y41",
      INIT => '0'
    )
    port map (
      I => Slave_i2cAddr_2_DXMUX_2514,
      CE => Slave_i2cAddr_2_CEINV_2505,
      CLK => Slave_i2cAddr_2_CLKINV_2506,
      SET => GND,
      RST => GND,
      O => Slave_i2cAddr(2)
    );
  Slave_ack_count_mux0000_10_1_SW0 : X_LUT4
    generic map(
      INIT => X"00AA",
      LOC => "SLICE_X23Y30"
    )
    port map (
      ADR0 => Slave_nstate_FFd1_1598,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Slave_ClkFallingEdge_1671,
      O => N8
    );
  Slave_i2cAddr_3 : X_FF
    generic map(
      LOC => "SLICE_X19Y39",
      INIT => '0'
    )
    port map (
      I => Slave_i2cAddr_4_DYMUX_2552,
      CE => Slave_i2cAddr_4_CEINV_2549,
      CLK => Slave_i2cAddr_4_CLKINV_2550,
      SET => GND,
      RST => GND,
      O => Slave_i2cAddr(3)
    );
  Slave_i2cAddr_4 : X_FF
    generic map(
      LOC => "SLICE_X19Y39",
      INIT => '0'
    )
    port map (
      I => Slave_i2cAddr_4_DXMUX_2558,
      CE => Slave_i2cAddr_4_CEINV_2549,
      CLK => Slave_i2cAddr_4_CLKINV_2550,
      SET => GND,
      RST => GND,
      O => Slave_i2cAddr(4)
    );
  Slave_nstate_FFd1_In9 : X_LUT4
    generic map(
      INIT => X"2A2A",
      LOC => "SLICE_X12Y39"
    )
    port map (
      ADR0 => Slave_nstate_FFd1_1598,
      ADR1 => Slave_DataRisingEdge_1595,
      ADR2 => OEM_I2C_Clk_IBUF_1604,
      ADR3 => VCC,
      O => Slave_nstate_FFd1_In9_2584
    );
  Slave_i2cAddr_5 : X_FF
    generic map(
      LOC => "SLICE_X18Y39",
      INIT => '0'
    )
    port map (
      I => Slave_i2cAddr_6_DYMUX_2596,
      CE => Slave_i2cAddr_6_CEINV_2593,
      CLK => Slave_i2cAddr_6_CLKINV_2594,
      SET => GND,
      RST => GND,
      O => Slave_i2cAddr(5)
    );
  Slave_i2cAddr_6 : X_FF
    generic map(
      LOC => "SLICE_X18Y39",
      INIT => '0'
    )
    port map (
      I => Slave_i2cAddr_6_DXMUX_2602,
      CE => Slave_i2cAddr_6_CEINV_2593,
      CLK => Slave_i2cAddr_6_CLKINV_2594,
      SET => GND,
      RST => GND,
      O => Slave_i2cAddr(6)
    );
  Slave_i2cAddr_7 : X_FF
    generic map(
      LOC => "SLICE_X19Y35",
      INIT => '0'
    )
    port map (
      I => Slave_i2cAddr_7_DYMUX_2614,
      CE => Slave_i2cAddr_7_CEINV_2611,
      CLK => Slave_i2cAddr_7_CLKINV_2612,
      SET => GND,
      RST => GND,
      O => Slave_i2cAddr(7)
    );
  Slave_shiftReg_mux0001_3_SW0 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X19Y40"
    )
    port map (
      ADR0 => Slave_N34,
      ADR1 => Slave_shiftReg(2),
      ADR2 => Slave_shiftReg(4),
      ADR3 => Slave_N39,
      O => N36
    );
  Slave_shiftReg_5 : X_SFF
    generic map(
      LOC => "SLICE_X19Y41",
      INIT => '0'
    )
    port map (
      I => Slave_shiftReg_5_DYMUX_2138,
      CE => VCC,
      CLK => Slave_shiftReg_5_CLKINV_2129,
      SET => GND,
      RST => GND,
      SSET => Slave_shiftReg_5_SRINV_2130,
      SRST => GND,
      O => Slave_shiftReg(5)
    );
  Slave_shiftReg_mux0001_4_SW0 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X19Y41"
    )
    port map (
      ADR0 => Slave_shiftReg(3),
      ADR1 => Slave_N34,
      ADR2 => Slave_shiftReg(5),
      ADR3 => Slave_N39,
      O => N34
    );
  Slave_delay_count_1 : X_FF
    generic map(
      LOC => "SLICE_X20Y19",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_1_DYMUX_2164,
      CE => VCC,
      CLK => Slave_delay_count_1_CLKINV_2156,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(1)
    );
  Slave_delay_count_2 : X_FF
    generic map(
      LOC => "SLICE_X22Y18",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_3_DYMUX_2187,
      CE => VCC,
      CLK => Slave_delay_count_3_CLKINV_2179,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(2)
    );
  Slave_delay_count_mux0000_3_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X22Y18"
    )
    port map (
      ADR0 => Slave_N3,
      ADR1 => Slave_delay_count(3),
      ADR2 => Slave_delay_count_or0000_1625,
      ADR3 => Slave_delay_count_share0000(3),
      O => Slave_delay_count_mux0000(3)
    );
  Slave_delay_count_3 : X_FF
    generic map(
      LOC => "SLICE_X22Y18",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_3_DXMUX_2198,
      CE => VCC,
      CLK => Slave_delay_count_3_CLKINV_2179,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(3)
    );
  Slave_delay_count_4 : X_FF
    generic map(
      LOC => "SLICE_X20Y18",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_5_DYMUX_2221,
      CE => VCC,
      CLK => Slave_delay_count_5_CLKINV_2213,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(4)
    );
  Slave_delay_count_mux0000_5_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X20Y18"
    )
    port map (
      ADR0 => Slave_delay_count_share0000(5),
      ADR1 => Slave_delay_count(5),
      ADR2 => Slave_N3,
      ADR3 => Slave_N17_0,
      O => Slave_delay_count_mux0000(5)
    );
  Slave_delay_count_5 : X_FF
    generic map(
      LOC => "SLICE_X20Y18",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_5_DXMUX_2232,
      CE => VCC,
      CLK => Slave_delay_count_5_CLKINV_2213,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(5)
    );
  Slave_delay_count_6 : X_FF
    generic map(
      LOC => "SLICE_X20Y21",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_7_DYMUX_2255,
      CE => VCC,
      CLK => Slave_delay_count_7_CLKINV_2247,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(6)
    );
  Slave_delay_count_mux0000_7_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X20Y21"
    )
    port map (
      ADR0 => Slave_delay_count(7),
      ADR1 => Slave_delay_count_share0000(7),
      ADR2 => Slave_N3,
      ADR3 => Slave_delay_count_or0000_1625,
      O => Slave_delay_count_mux0000(7)
    );
  Slave_delay_count_7 : X_FF
    generic map(
      LOC => "SLICE_X20Y21",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_7_DXMUX_2266,
      CE => VCC,
      CLK => Slave_delay_count_7_CLKINV_2247,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(7)
    );
  Slave_delay_count_8 : X_FF
    generic map(
      LOC => "SLICE_X23Y20",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_9_DYMUX_2289,
      CE => VCC,
      CLK => Slave_delay_count_9_CLKINV_2281,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(8)
    );
  Slave_delay_count_mux0000_9_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X23Y20"
    )
    port map (
      ADR0 => Slave_delay_count(9),
      ADR1 => Slave_delay_count_share0000(9),
      ADR2 => Slave_N3,
      ADR3 => Slave_delay_count_or0000_1625,
      O => Slave_delay_count_mux0000(9)
    );
  Slave_delay_count_9 : X_FF
    generic map(
      LOC => "SLICE_X23Y20",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_9_DXMUX_2300,
      CE => VCC,
      CLK => Slave_delay_count_9_CLKINV_2281,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(9)
    );
  Slave_pstate_FFd3_In80_SW1_F : X_LUT4
    generic map(
      INIT => X"5500",
      LOC => "SLICE_X17Y37"
    )
    port map (
      ADR0 => Slave_Mcompar_pstate_cmp_gt0000_cy_5_Q,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Slave_nstate_FFd2_1691,
      O => N161
    );
  Slave_delay_count_mux0000_0_162 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X22Y20"
    )
    port map (
      ADR0 => Slave_delay_count(8),
      ADR1 => Slave_delay_count(3),
      ADR2 => Slave_delay_count(0),
      ADR3 => Slave_delay_count(9),
      O => Slave_delay_count_mux0000_0_162_2664
    );
  Slave_done : X_FF
    generic map(
      LOC => "SLICE_X15Y30",
      INIT => '0'
    )
    port map (
      I => Slave_done_DYMUX_2674,
      CE => Slave_done_CEINV_2671,
      CLK => Slave_done_CLKINV_2672,
      SET => GND,
      RST => GND,
      O => Slave_done_1655
    );
  Slave_counter_mux0000_0_SW2 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X15Y29"
    )
    port map (
      ADR0 => Slave_counter(4),
      ADR1 => Slave_ClkRisingEdge_1699,
      ADR2 => Slave_nstate_FFd3_1642,
      ADR3 => Slave_Madd_counter_addsub0000_cy(3),
      O => N135
    );
  Slave_pstate_FFd2_In9 : X_LUT4
    generic map(
      INIT => X"CE0A",
      LOC => "SLICE_X14Y40"
    )
    port map (
      ADR0 => Slave_pstate_FFd1_1706,
      ADR1 => OEM_I2C_Clk_IBUF_1604,
      ADR2 => Slave_pstate_FFd3_1644,
      ADR3 => Slave_DataRisingEdge_1595,
      O => Slave_pstate_FFd2_In9_2724
    );
  Slave_ack_count_mux0000_10_111 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X17Y36"
    )
    port map (
      ADR0 => Slave_nstate_FFd5_1646,
      ADR1 => Slave_nstate_FFd7_1710,
      ADR2 => Slave_nstate_FFd6_1709,
      ADR3 => Slave_nstate_FFd2_1691,
      O => Slave_N28
    );
  Slave_shiftReg_mux0001_0_2_SW0 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X21Y38"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_nstate_FFd2_1691,
      ADR2 => VCC,
      ADR3 => Slave_ClkFallingEdge_1671,
      O => N28
    );
  Slave_counter_mux0000_4_17 : X_LUT4
    generic map(
      INIT => X"0505",
      LOC => "SLICE_X13Y35"
    )
    port map (
      ADR0 => Slave_counter(5),
      ADR1 => VCC,
      ADR2 => Slave_counter(2),
      ADR3 => VCC,
      O => Slave_counter_mux0000_4_17_2796
    );
  Slave_nstate_FFd5 : X_SFF
    generic map(
      LOC => "SLICE_X16Y39",
      INIT => '0'
    )
    port map (
      I => Slave_nstate_FFd5_DYMUX_2323,
      CE => VCC,
      CLK => Slave_nstate_FFd5_CLKINV_2313,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => Slave_nstate_FFd5_SRINV_2314,
      O => Slave_nstate_FFd5_1646
    );
  Slave_i2cAddr_not00011 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X16Y39"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_nstate_FFd3_1642,
      ADR2 => VCC,
      ADR3 => Slave_pstate_cmp_eq0002_0,
      O => Slave_i2cAddr_not0001
    );
  Slave_pstate_FFd2_In219_SW0 : X_LUT4
    generic map(
      INIT => X"AA00",
      LOC => "SLICE_X14Y41"
    )
    port map (
      ADR0 => Slave_pstate_FFd2_In121_1647,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Slave_pstate_FFd2_1641,
      O => N98
    );
  Slave_pstate_FFd2_In81_SW0 : X_LUT4
    generic map(
      INIT => X"AFAF",
      LOC => "SLICE_X15Y31"
    )
    port map (
      ADR0 => Slave_counter(2),
      ADR1 => VCC,
      ADR2 => Slave_nstate_FFd1_1598,
      ADR3 => VCC,
      O => N74
    );
  Slave_doutvalid_mux0000211_SW0 : X_LUT4
    generic map(
      INIT => X"DDFF",
      LOC => "SLICE_X16Y30"
    )
    port map (
      ADR0 => OEM_I2C_Clk_IBUF_1604,
      ADR1 => Slave_done_1655,
      ADR2 => VCC,
      ADR3 => Slave_DataRisingEdge_1595,
      O => N169
    );
  Slave_ack_count_cmp_eq00001_SW3 : X_LUT4
    generic map(
      INIT => X"EFEF",
      LOC => "SLICE_X23Y34"
    )
    port map (
      ADR0 => Slave_ack_count(4),
      ADR1 => Slave_ack_count(2),
      ADR2 => Slave_ack_count(1),
      ADR3 => VCC,
      O => N96
    );
  Slave_prevClk_mux00001 : X_LUT4
    generic map(
      INIT => X"E8E8",
      LOC => "SLICE_X19Y36"
    )
    port map (
      ADR0 => Slave_ClkEdge(1),
      ADR1 => Slave_ClkEdge(0),
      ADR2 => Slave_prevClk_1667,
      ADR3 => VCC,
      O => Slave_prevClk_mux0000
    );
  Slave_prevClk : X_FF
    generic map(
      LOC => "SLICE_X19Y36",
      INIT => '0'
    )
    port map (
      I => Slave_prevClk_DXMUX_2459,
      CE => VCC,
      CLK => Slave_prevClk_CLKINV_2442,
      SET => GND,
      RST => GND,
      O => Slave_prevClk_1667
    );
  Slave_ClkFallingEdge : X_SFF
    generic map(
      LOC => "SLICE_X21Y37",
      INIT => '0'
    )
    port map (
      I => Slave_ClkFallingEdge_DYMUX_2470,
      CE => VCC,
      CLK => Slave_ClkFallingEdge_CLKINV_2467,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => Slave_ClkFallingEdge_SRINV_2468,
      O => Slave_ClkFallingEdge_1671
    );
  Slave_shiftReg_mux0001_2_SW0 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X17Y40"
    )
    port map (
      ADR0 => Slave_N34,
      ADR1 => Slave_shiftReg(3),
      ADR2 => Slave_shiftReg(1),
      ADR3 => Slave_N39,
      O => N38
    );
  Slave_nstate_FFd4_In28 : X_LUT4
    generic map(
      INIT => X"EECC",
      LOC => "SLICE_X17Y39"
    )
    port map (
      ADR0 => Slave_Mcompar_pstate_cmp_gt0000_cy_5_Q,
      ADR1 => Slave_nstate_FFd7_1710,
      ADR2 => VCC,
      ADR3 => Slave_nstate_FFd2_1691,
      O => Slave_nstate_FFd4_In28_2844
    );
  Slave_delay_count_mux0000_0_31_SW0 : X_LUT4
    generic map(
      INIT => X"0404",
      LOC => "SLICE_X21Y35"
    )
    port map (
      ADR0 => Slave_delay_count(5),
      ADR1 => Slave_nstate_FFd2_1691,
      ADR2 => Slave_ClkFallingEdge_1671,
      ADR3 => VCC,
      O => N92
    );
  Slave_Dir_mux000080 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X22Y26"
    )
    port map (
      ADR0 => Slave_delay_count(9),
      ADR1 => Slave_delay_count(2),
      ADR2 => Slave_delay_count(3),
      ADR3 => Slave_delay_count(8),
      O => Slave_Dir_mux000080_2892
    );
  Slave_counter_mux0000_3_SW2 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X16Y29"
    )
    port map (
      ADR0 => Slave_ClkRisingEdge_1699,
      ADR1 => Slave_counter(0),
      ADR2 => Slave_nstate_FFd3_1642,
      ADR3 => Slave_counter(1),
      O => N132
    );
  Slave_ClkEdge_0 : X_FF
    generic map(
      LOC => "SLICE_X19Y37",
      INIT => '1'
    )
    port map (
      I => Slave_ClkEdge_1_DYMUX_2926,
      CE => VCC,
      CLK => Slave_ClkEdge_1_CLKINV_2924,
      SET => GND,
      RST => GND,
      O => Slave_ClkEdge(0)
    );
  Slave_ClkEdge_1 : X_FF
    generic map(
      LOC => "SLICE_X19Y37",
      INIT => '1'
    )
    port map (
      I => Slave_ClkEdge_1_DXMUX_2931,
      CE => VCC,
      CLK => Slave_ClkEdge_1_CLKINV_2924,
      SET => GND,
      RST => GND,
      O => Slave_ClkEdge(1)
    );
  Slave_Dir_mux000069 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X21Y27"
    )
    port map (
      ADR0 => Slave_delay_count(0),
      ADR1 => Slave_delay_count(7),
      ADR2 => Slave_delay_count(11),
      ADR3 => Slave_delay_count(4),
      O => Slave_Dir_mux000069_2956
    );
  Slave_Dir_mux000064 : X_LUT4
    generic map(
      INIT => X"AFAF",
      LOC => "SLICE_X21Y26"
    )
    port map (
      ADR0 => Slave_delay_count(10),
      ADR1 => VCC,
      ADR2 => Slave_delay_count(5),
      ADR3 => VCC,
      O => Slave_Dir_mux000064_2980
    );
  Slave_pstate_FFd2_In159_SW0 : X_LUT4
    generic map(
      INIT => X"FDFE",
      LOC => "SLICE_X14Y33"
    )
    port map (
      ADR0 => Slave_counter(0),
      ADR1 => Slave_counter(1),
      ADR2 => Slave_counter(2),
      ADR3 => Slave_counter(3),
      O => N85
    );
  Slave_counter_mux0000_4_451 : X_LUT4
    generic map(
      INIT => X"88A8",
      LOC => "SLICE_X16Y33"
    )
    port map (
      ADR0 => Slave_counter(1),
      ADR1 => Slave_N241,
      ADR2 => Slave_nstate_FFd3_1642,
      ADR3 => Slave_counter(0),
      O => Slave_counter_mux0000_4_45
    );
  Slave_counter_1 : X_SFF
    generic map(
      LOC => "SLICE_X16Y33",
      INIT => '1'
    )
    port map (
      I => Slave_counter_1_DXMUX_3035,
      CE => VCC,
      CLK => Slave_counter_1_CLKINV_3019,
      SET => GND,
      RST => GND,
      SSET => Slave_counter_1_SRINV_3020,
      SRST => GND,
      O => Slave_counter(1)
    );
  Slave_counter_0 : X_SFF
    generic map(
      LOC => "SLICE_X17Y31",
      INIT => '1'
    )
    port map (
      I => Slave_counter_0_DYMUX_3047,
      CE => VCC,
      CLK => Slave_counter_0_CLKINV_3044,
      SET => GND,
      RST => GND,
      SSET => Slave_counter_0_SRINV_3045,
      SRST => GND,
      O => Slave_counter(0)
    );
  Slave_shiftReg_mux0001_5_SW0 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X19Y38"
    )
    port map (
      ADR0 => Slave_shiftReg(6),
      ADR1 => Slave_N34,
      ADR2 => Slave_shiftReg(4),
      ADR3 => Slave_N39,
      O => N32
    );
  Slave_in_i2c_mux0000111 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X22Y32"
    )
    port map (
      ADR0 => Slave_ack_count(0),
      ADR1 => Slave_ack_count(8),
      ADR2 => Slave_ack_count(5),
      ADR3 => Slave_ack_count(6),
      O => Slave_N261
    );
  Slave_pstate_FFd3_In80_SW1_G : X_LUT4
    generic map(
      INIT => X"4F44",
      LOC => "SLICE_X15Y40"
    )
    port map (
      ADR0 => Slave_pstate_FFd2_1641,
      ADR1 => Slave_nstate_FFd3_1642,
      ADR2 => Slave_Mcompar_pstate_cmp_gt0000_cy_5_Q,
      ADR3 => Slave_nstate_FFd2_1691,
      O => N162
    );
  Slave_nstate_FFd7_In : X_LUT4
    generic map(
      INIT => X"30BA",
      LOC => "SLICE_X19Y33"
    )
    port map (
      ADR0 => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1,
      ADR1 => Slave_Mcompar_pstate_cmp_gt0000_cy_5_Q,
      ADR2 => Slave_nstate_FFd2_1691,
      ADR3 => N6,
      O => Slave_nstate_FFd7_In_3147
    );
  Slave_nstate_FFd7 : X_FF
    generic map(
      LOC => "SLICE_X19Y33",
      INIT => '0'
    )
    port map (
      I => Slave_nstate_FFd7_DXMUX_3150,
      CE => VCC,
      CLK => Slave_nstate_FFd7_CLKINV_3134,
      SET => GND,
      RST => GND,
      O => Slave_nstate_FFd7_1710
    );
  Slave_ack_count_mux0000_8_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X22Y35"
    )
    port map (
      ADR0 => Slave_ack_count(8),
      ADR1 => Slave_N40_0,
      ADR2 => Slave_N0,
      ADR3 => Slave_ack_count_addsub0000(8),
      O => Slave_ack_count_mux0000(8)
    );
  Slave_ack_count_8 : X_FF
    generic map(
      LOC => "SLICE_X22Y35",
      INIT => '0'
    )
    port map (
      I => Slave_ack_count_8_DXMUX_3204,
      CE => VCC,
      CLK => Slave_ack_count_8_CLKINV_3189,
      SET => GND,
      RST => GND,
      O => Slave_ack_count(8)
    );
  Slave_counter_mux0000_3_Q : X_LUT4
    generic map(
      INIT => X"FAD8",
      LOC => "SLICE_X17Y29"
    )
    port map (
      ADR0 => Slave_counter(2),
      ADR1 => Slave_N18_0,
      ADR2 => N132_0,
      ADR3 => N133,
      O => Slave_counter_mux0000_3_Q_3243
    );
  Slave_counter_2 : X_FF
    generic map(
      LOC => "SLICE_X17Y29",
      INIT => '0'
    )
    port map (
      I => Slave_counter_2_DXMUX_3246,
      CE => VCC,
      CLK => Slave_counter_2_CLKINV_3231,
      SET => GND,
      RST => GND,
      O => Slave_counter(2)
    );
  Slave_DataFallingEdge : X_SFF
    generic map(
      LOC => "SLICE_X15Y43",
      INIT => '0'
    )
    port map (
      I => Slave_DataFallingEdge_DYMUX_3257,
      CE => VCC,
      CLK => Slave_DataFallingEdge_CLKINV_3254,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => Slave_DataFallingEdge_SRINV_3255,
      O => Slave_DataFallingEdge_1605
    );
  Slave_Madd_delay_count_share0000_lut_0_INV_0 : X_LUT4
    generic map(
      INIT => X"00FF",
      LOC => "SLICE_X21Y17"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Slave_delay_count(0),
      O => Slave_Madd_delay_count_share0000_lut(0)
    );
  Slave_edge_0 : X_FF
    generic map(
      LOC => "SLICE_X15Y44",
      INIT => '1'
    )
    port map (
      I => Slave_edge_1_DYMUX_3317,
      CE => VCC,
      CLK => Slave_edge_1_CLKINV_3315,
      SET => GND,
      RST => GND,
      O => Slave_edge(0)
    );
  Slave_edge_1 : X_FF
    generic map(
      LOC => "SLICE_X15Y44",
      INIT => '1'
    )
    port map (
      I => Slave_edge_1_DXMUX_3322,
      CE => VCC,
      CLK => Slave_edge_1_CLKINV_3315,
      SET => GND,
      RST => GND,
      O => Slave_edge(1)
    );
  Slave_delay_count_11_rt_1 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X19Y25"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Slave_delay_count(11),
      ADR3 => VCC,
      O => Slave_delay_count_11_rt
    );
  Slave_Madd_ack_count_addsub0000_lut_0_INV_0 : X_LUT4
    generic map(
      INIT => X"3333",
      LOC => "SLICE_X25Y30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_ack_count(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_Madd_ack_count_addsub0000_lut(0)
    );
  Slave_Mcompar_pstate_cmp_gt0000_lut_2_1 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X19Y22"
    )
    port map (
      ADR0 => Slave_delay_count(11),
      ADR1 => Slave_delay_count(12),
      ADR2 => Slave_delay_count(9),
      ADR3 => Slave_delay_count(10),
      O => Slave_Mcompar_pstate_cmp_gt0000_lut_2_1_3639
    );
  Slave_Mcompar_pstate_cmp_gt0000_lut_0_Q : X_LUT4
    generic map(
      INIT => X"0303",
      LOC => "SLICE_X19Y23"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_delay_count(1),
      ADR2 => Slave_delay_count(0),
      ADR3 => VCC,
      O => Slave_Mcompar_pstate_cmp_gt0000_lut_0_Q_3664
    );
  Slave_Mcompar_pstate_cmp_gt0000_lut_2_Q : X_LUT4
    generic map(
      INIT => X"0033",
      LOC => "SLICE_X19Y24"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_delay_count(5),
      ADR2 => VCC,
      ADR3 => Slave_delay_count(6),
      O => Slave_Mcompar_pstate_cmp_gt0000_lut_2_Q_3697
    );
  Slave_pstate_FFd3_In1221 : X_LUT4
    generic map(
      INIT => X"AAA8",
      LOC => "SLICE_X15Y37"
    )
    port map (
      ADR0 => Slave_pstate_FFd3_1644,
      ADR1 => N70_0,
      ADR2 => Slave_doutvalid_mux00001_0,
      ADR3 => Slave_pstate_FFd1_In1313_1858,
      O => Slave_pstate_FFd3_In122
    );
  Slave_pstate_FFd3 : X_SFF
    generic map(
      LOC => "SLICE_X15Y37",
      INIT => '0'
    )
    port map (
      I => Slave_pstate_FFd3_DXMUX_4833,
      CE => VCC,
      CLK => Slave_pstate_FFd3_CLKINV_4817,
      SET => GND,
      RST => GND,
      SSET => Slave_pstate_FFd3_SRINV_4818,
      SRST => GND,
      O => Slave_pstate_FFd3_1644
    );
  Slave_ack_count_mux0000_0_21 : X_LUT4
    generic map(
      INIT => X"0A0A",
      LOC => "SLICE_X22Y33"
    )
    port map (
      ADR0 => Slave_nstate_FFd1_1598,
      ADR1 => VCC,
      ADR2 => Slave_ack_count_cmp_eq0000_1679,
      ADR3 => VCC,
      O => Slave_N40
    );
  Slave_Dir_mux00001601_SW0 : X_LUT4
    generic map(
      INIT => X"FFD0",
      LOC => "SLICE_X20Y32"
    )
    port map (
      ADR0 => Slave_Dir_and0000_0,
      ADR1 => Slave_N261_0,
      ADR2 => Slave_nstate_FFd1_1598,
      ADR3 => Slave_N291,
      O => N88
    );
  Slave_Dir_mux000021 : X_LUT4
    generic map(
      INIT => X"A000",
      LOC => "SLICE_X23Y33"
    )
    port map (
      ADR0 => Slave_ack_count(0),
      ADR1 => VCC,
      ADR2 => Slave_nstate_FFd1_1598,
      ADR3 => Slave_N45,
      O => Slave_Dir_mux00002
    );
  Slave_Dir_mux000051 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X20Y26"
    )
    port map (
      ADR0 => Slave_Dir_mux00002_0,
      ADR1 => Slave_N36_0,
      ADR2 => Slave_Dir_and0000_0,
      ADR3 => Slave_Dir_mux000039_SW0_O,
      O => Slave_Dir_mux000051_4931
    );
  Slave_shiftReg_mux0001_0_111 : X_LUT4
    generic map(
      INIT => X"FCFE",
      LOC => "SLICE_X18Y31"
    )
    port map (
      ADR0 => Slave_nstate_FFd3_1642,
      ADR1 => Slave_nstate_FFd1_1598,
      ADR2 => Slave_N32,
      ADR3 => Slave_ClkRisingEdge_1699,
      O => Slave_N18
    );
  Slave_delay_count_mux0000_12_11 : X_LUT4
    generic map(
      INIT => X"F8F0",
      LOC => "SLICE_X21Y31"
    )
    port map (
      ADR0 => N92_0,
      ADR1 => Slave_N36_0,
      ADR2 => Slave_delay_count_or0000_1625,
      ADR3 => Slave_delay_count_cmp_eq0000_0,
      O => Slave_N17
    );
  Slave_counter_mux0000_2_SW0 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X14Y31"
    )
    port map (
      ADR0 => Slave_counter(1),
      ADR1 => Slave_counter(0),
      ADR2 => Slave_N39,
      ADR3 => Slave_counter(2),
      O => N25
    );
  Slave_counter_4 : X_FF
    generic map(
      LOC => "SLICE_X14Y28",
      INIT => '0'
    )
    port map (
      I => Slave_counter_4_DXMUX_4517,
      CE => VCC,
      CLK => Slave_counter_4_CLKINV_4501,
      SET => GND,
      RST => GND,
      O => Slave_counter(4)
    );
  Slave_nstate_FFd6_In2 : X_LUT4
    generic map(
      INIT => X"0200",
      LOC => "SLICE_X17Y30"
    )
    port map (
      ADR0 => Slave_counter(5),
      ADR1 => N56,
      ADR2 => Slave_nstate_FFd6_In2_SW1_O,
      ADR3 => Slave_pstate_cmp_eq0008_0,
      O => Slave_nstate_FFd6_In
    );
  Slave_nstate_FFd6 : X_FF
    generic map(
      LOC => "SLICE_X17Y30",
      INIT => '0'
    )
    port map (
      I => Slave_nstate_FFd6_DXMUX_4548,
      CE => VCC,
      CLK => Slave_nstate_FFd6_CLKINV_4533,
      SET => GND,
      RST => GND,
      O => Slave_nstate_FFd6_1709
    );
  Slave_shiftReg_cmp_eq0000234 : X_LUT4
    generic map(
      INIT => X"0400",
      LOC => "SLICE_X20Y20"
    )
    port map (
      ADR0 => Slave_delay_count(7),
      ADR1 => Slave_shiftReg_cmp_eq000028_0,
      ADR2 => Slave_delay_count(4),
      ADR3 => Slave_shiftReg_cmp_eq0000232_O,
      O => Slave_delay_count_cmp_eq0000
    );
  Slave_pstate_FFd1_In112 : X_LUT4
    generic map(
      INIT => X"110A",
      LOC => "SLICE_X15Y32"
    )
    port map (
      ADR0 => Slave_counter(5),
      ADR1 => N85_0,
      ADR2 => N86,
      ADR3 => Slave_counter(4),
      O => Slave_N38
    );
  Slave_doutvalid_mux0000571 : X_LUT4
    generic map(
      INIT => X"CC80",
      LOC => "SLICE_X16Y26"
    )
    port map (
      ADR0 => Slave_nstate_FFd4_1597,
      ADR1 => Slave_doutvalid_1817,
      ADR2 => Slave_N211_0,
      ADR3 => Slave_doutvalid_mux0000211_O,
      O => Slave_doutvalid_mux000057
    );
  Slave_doutvalid : X_SFF
    generic map(
      LOC => "SLICE_X16Y26",
      INIT => '0'
    )
    port map (
      I => Slave_doutvalid_DXMUX_4628,
      CE => VCC,
      CLK => Slave_doutvalid_CLKINV_4612,
      SET => GND,
      RST => GND,
      SSET => Slave_doutvalid_SRINV_4613,
      SRST => GND,
      O => Slave_doutvalid_1817
    );
  Slave_counter_mux0000_5_451 : X_LUT4
    generic map(
      INIT => X"A8A8",
      LOC => "SLICE_X16Y31"
    )
    port map (
      ADR0 => Slave_counter(0),
      ADR1 => Slave_N28_0,
      ADR2 => Slave_counter_mux0000_5_29_O,
      ADR3 => VCC,
      O => Slave_counter_mux0000_5_45
    );
  Slave_counter_0_1 : X_SFF
    generic map(
      LOC => "SLICE_X16Y31",
      INIT => '1'
    )
    port map (
      I => Slave_counter_0_1_DXMUX_4662,
      CE => VCC,
      CLK => Slave_counter_0_1_CLKINV_4645,
      SET => GND,
      RST => GND,
      SSET => Slave_counter_0_1_SRINV_4646,
      SRST => GND,
      O => Slave_counter_0_1_1851
    );
  Slave_shiftReg_mux0001_6_SW0 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X20Y39"
    )
    port map (
      ADR0 => Slave_shiftReg(5),
      ADR1 => Slave_shiftReg(7),
      ADR2 => Slave_N34,
      ADR3 => Slave_N39,
      O => N30
    );
  Slave_pstate_FFd2_In2451 : X_LUT4
    generic map(
      INIT => X"FFD8",
      LOC => "SLICE_X14Y36"
    )
    port map (
      ADR0 => Slave_pstate_FFd2_In192_0,
      ADR1 => N99_0,
      ADR2 => N98_0,
      ADR3 => Slave_pstate_FFd2_In91_O,
      O => Slave_pstate_FFd2_In245
    );
  Slave_pstate_FFd2 : X_SFF
    generic map(
      LOC => "SLICE_X14Y36",
      INIT => '0'
    )
    port map (
      I => Slave_pstate_FFd2_DXMUX_4719,
      CE => VCC,
      CLK => Slave_pstate_FFd2_CLKINV_4703,
      SET => GND,
      RST => GND,
      SSET => Slave_pstate_FFd2_SRINV_4704,
      SRST => GND,
      O => Slave_pstate_FFd2_1641
    );
  Slave_pstate_FFd1_In401 : X_LUT4
    generic map(
      INIT => X"CCC8",
      LOC => "SLICE_X14Y38"
    )
    port map (
      ADR0 => Slave_pstate_FFd1_In1313_1858,
      ADR1 => Slave_pstate_FFd1_1706,
      ADR2 => N70_0,
      ADR3 => Slave_pstate_FFd1_In26_O,
      O => Slave_pstate_FFd1_In40
    );
  Slave_pstate_FFd1 : X_SFF
    generic map(
      LOC => "SLICE_X14Y38",
      INIT => '0'
    )
    port map (
      I => Slave_pstate_FFd1_DXMUX_4752,
      CE => VCC,
      CLK => Slave_pstate_FFd1_CLKINV_4736,
      SET => GND,
      RST => GND,
      SSET => Slave_pstate_FFd1_SRINV_4737,
      SRST => GND,
      O => Slave_pstate_FFd1_1706
    );
  Slave_pstate_FFd2_In33 : X_LUT4
    generic map(
      INIT => X"0008",
      LOC => "SLICE_X14Y30"
    )
    port map (
      ADR0 => Slave_counter(1),
      ADR1 => Slave_counter(5),
      ADR2 => Slave_counter(0),
      ADR3 => N56,
      O => Slave_N391
    );
  Slave_pstate_FFd3_In80_SW0 : X_LUT4
    generic map(
      INIT => X"FFAE",
      LOC => "SLICE_X15Y35"
    )
    port map (
      ADR0 => Slave_pstate_FFd3_1644,
      ADR1 => Slave_N391_0,
      ADR2 => Slave_counter(2),
      ADR3 => Slave_pstate_FFd3_In50_O,
      O => N60
    );
  Slave_delay_count_mux0000_15_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X20Y25"
    )
    port map (
      ADR0 => Slave_delay_count(15),
      ADR1 => Slave_delay_count_share0000(15),
      ADR2 => Slave_N3,
      ADR3 => Slave_N17_0,
      O => Slave_delay_count_mux0000(15)
    );
  Slave_delay_count_15 : X_FF
    generic map(
      LOC => "SLICE_X20Y25",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_15_DXMUX_6025,
      CE => VCC,
      CLK => Slave_delay_count_15_CLKINV_6006,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(15)
    );
  Slave_ack_count_10 : X_FF
    generic map(
      LOC => "SLICE_X24Y34",
      INIT => '0'
    )
    port map (
      I => Slave_ack_count_11_DYMUX_6048,
      CE => VCC,
      CLK => Slave_ack_count_11_CLKINV_6040,
      SET => GND,
      RST => GND,
      O => Slave_ack_count(10)
    );
  Slave_ack_count_mux0000_11_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X24Y34"
    )
    port map (
      ADR0 => Slave_ack_count_addsub0000(11),
      ADR1 => Slave_ack_count(11),
      ADR2 => Slave_N0,
      ADR3 => Slave_N40_0,
      O => Slave_ack_count_mux0000(11)
    );
  Slave_ack_count_11 : X_FF
    generic map(
      LOC => "SLICE_X24Y34",
      INIT => '0'
    )
    port map (
      I => Slave_ack_count_11_DXMUX_6059,
      CE => VCC,
      CLK => Slave_ack_count_11_CLKINV_6040,
      SET => GND,
      RST => GND,
      O => Slave_ack_count(11)
    );
  Slave_ack_count_1 : X_FF
    generic map(
      LOC => "SLICE_X24Y31",
      INIT => '0'
    )
    port map (
      I => Slave_ack_count_1_DYMUX_6077,
      CE => VCC,
      CLK => Slave_ack_count_1_CLKINV_6069,
      SET => GND,
      RST => GND,
      O => Slave_ack_count(1)
    );
  Slave_ack_count_2 : X_FF
    generic map(
      LOC => "SLICE_X24Y30",
      INIT => '0'
    )
    port map (
      I => Slave_ack_count_3_DYMUX_6100,
      CE => VCC,
      CLK => Slave_ack_count_3_CLKINV_6092,
      SET => GND,
      RST => GND,
      O => Slave_ack_count(2)
    );
  Slave_ack_count_mux0000_3_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X24Y30"
    )
    port map (
      ADR0 => Slave_ack_count_addsub0000(3),
      ADR1 => Slave_N0,
      ADR2 => Slave_N40_0,
      ADR3 => Slave_ack_count(3),
      O => Slave_ack_count_mux0000(3)
    );
  Slave_ack_count_3 : X_FF
    generic map(
      LOC => "SLICE_X24Y30",
      INIT => '0'
    )
    port map (
      I => Slave_ack_count_3_DXMUX_6111,
      CE => VCC,
      CLK => Slave_ack_count_3_CLKINV_6092,
      SET => GND,
      RST => GND,
      O => Slave_ack_count(3)
    );
  Slave_ack_count_4 : X_FF
    generic map(
      LOC => "SLICE_X24Y33",
      INIT => '0'
    )
    port map (
      I => Slave_ack_count_5_DYMUX_6134,
      CE => VCC,
      CLK => Slave_ack_count_5_CLKINV_6126,
      SET => GND,
      RST => GND,
      O => Slave_ack_count(4)
    );
  Slave_ack_count_mux0000_5_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X24Y33"
    )
    port map (
      ADR0 => Slave_N0,
      ADR1 => Slave_ack_count_addsub0000(5),
      ADR2 => Slave_ack_count(5),
      ADR3 => Slave_N40_0,
      O => Slave_ack_count_mux0000(5)
    );
  Slave_ack_count_5 : X_FF
    generic map(
      LOC => "SLICE_X24Y33",
      INIT => '0'
    )
    port map (
      I => Slave_ack_count_5_DXMUX_6145,
      CE => VCC,
      CLK => Slave_ack_count_5_CLKINV_6126,
      SET => GND,
      RST => GND,
      O => Slave_ack_count(5)
    );
  Slave_ack_count_6 : X_FF
    generic map(
      LOC => "SLICE_X24Y32",
      INIT => '0'
    )
    port map (
      I => Slave_ack_count_7_DYMUX_6168,
      CE => VCC,
      CLK => Slave_ack_count_7_CLKINV_6160,
      SET => GND,
      RST => GND,
      O => Slave_ack_count(6)
    );
  Slave_ack_count_mux0000_7_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X24Y32"
    )
    port map (
      ADR0 => Slave_ack_count_addsub0000(7),
      ADR1 => Slave_N0,
      ADR2 => Slave_N40_0,
      ADR3 => Slave_ack_count(7),
      O => Slave_ack_count_mux0000(7)
    );
  Slave_ack_count_7 : X_FF
    generic map(
      LOC => "SLICE_X24Y32",
      INIT => '0'
    )
    port map (
      I => Slave_ack_count_7_DXMUX_6179,
      CE => VCC,
      CLK => Slave_ack_count_7_CLKINV_6160,
      SET => GND,
      RST => GND,
      O => Slave_ack_count(7)
    );
  Slave_delay_count_mux0000_0_1 : X_LUT4
    generic map(
      INIT => X"F000",
      LOC => "SLICE_X18Y21"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Slave_N3,
      ADR3 => Slave_delay_count_share0000(0),
      O => Slave_delay_count_mux0000_0_1_5031
    );
  Slave_delay_count_0 : X_SFF
    generic map(
      LOC => "SLICE_X18Y21",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_0_DXMUX_5034,
      CE => VCC,
      CLK => Slave_delay_count_0_CLKINV_5016,
      SET => GND,
      RST => GND,
      SSET => Slave_delay_count_0_SRINV_5017,
      SRST => GND,
      O => Slave_delay_count(0)
    );
  Slave_pstate_cmp_eq0002 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X17Y32"
    )
    port map (
      ADR0 => Slave_counter(4),
      ADR1 => Slave_counter(5),
      ADR2 => N52,
      ADR3 => Slave_counter(1),
      O => Slave_pstate_cmp_eq0002_5060
    );
  Slave_nstate_FFd2_In : X_LUT4
    generic map(
      INIT => X"5D55",
      LOC => "SLICE_X17Y35"
    )
    port map (
      ADR0 => N10_0,
      ADR1 => Slave_pstate_cmp_eq0009,
      ADR2 => Slave_i2cAddr(7),
      ADR3 => Slave_N46,
      O => Slave_nstate_FFd2_In_5086
    );
  Slave_nstate_FFd2 : X_FF
    generic map(
      LOC => "SLICE_X17Y35",
      INIT => '0'
    )
    port map (
      I => Slave_nstate_FFd2_DXMUX_5089,
      CE => VCC,
      CLK => Slave_nstate_FFd2_CLKINV_5072,
      SET => GND,
      RST => GND,
      O => Slave_nstate_FFd2_1691
    );
  Slave_pstate_cmp_eq0008 : X_LUT4
    generic map(
      INIT => X"0100",
      LOC => "SLICE_X23Y32"
    )
    port map (
      ADR0 => N76_0,
      ADR1 => Slave_ack_count(3),
      ADR2 => Slave_pstate_cmp_eq0008_SW1_O,
      ADR3 => Slave_N45,
      O => Slave_pstate_cmp_eq0008_5114
    );
  Slave_nstate_FFd1_In271 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X15Y36"
    )
    port map (
      ADR0 => Slave_nstate_FFd3_1642,
      ADR1 => Slave_nstate_FFd1_In9_0,
      ADR2 => Slave_nstate_FFd1_In8_O,
      ADR3 => Slave_N38_0,
      O => Slave_nstate_FFd1_In27
    );
  Slave_nstate_FFd1 : X_SFF
    generic map(
      LOC => "SLICE_X15Y36",
      INIT => '0'
    )
    port map (
      I => Slave_nstate_FFd1_DXMUX_5145,
      CE => VCC,
      CLK => Slave_nstate_FFd1_CLKINV_5129,
      SET => GND,
      RST => GND,
      SSET => Slave_nstate_FFd1_SRINV_5130,
      SRST => GND,
      O => Slave_nstate_FFd1_1598
    );
  Slave_nstate_FFd6_In11 : X_LUT4
    generic map(
      INIT => X"FFFC",
      LOC => "SLICE_X14Y35"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_counter(2),
      ADR2 => N130,
      ADR3 => Slave_counter(5),
      O => Slave_N401
    );
  Slave_pstate_FFd3_In28 : X_LUT4
    generic map(
      INIT => X"FFF2",
      LOC => "SLICE_X15Y39"
    )
    port map (
      ADR0 => Slave_nstate_FFd7_1710,
      ADR1 => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1,
      ADR2 => Slave_nstate_FFd5_1646,
      ADR3 => Slave_pstate_FFd3_In21_SW1_O,
      O => Slave_pstate_FFd3_In28_5195
    );
  Slave_ack_count_mux0000_9_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X23Y31"
    )
    port map (
      ADR0 => Slave_ack_count(9),
      ADR1 => Slave_ack_count_addsub0000(9),
      ADR2 => Slave_N40_0,
      ADR3 => Slave_N0,
      O => Slave_ack_count_mux0000(9)
    );
  Slave_ack_count_9 : X_FF
    generic map(
      LOC => "SLICE_X23Y31",
      INIT => '0'
    )
    port map (
      I => Slave_ack_count_9_DXMUX_5224,
      CE => VCC,
      CLK => Slave_ack_count_9_CLKINV_5209,
      SET => GND,
      RST => GND,
      O => Slave_ack_count(9)
    );
  Slave_nstate_FFd3_In41 : X_LUT4
    generic map(
      INIT => X"FFA8",
      LOC => "SLICE_X16Y35"
    )
    port map (
      ADR0 => Slave_N46,
      ADR1 => Slave_nstate_FFd3_In18_0,
      ADR2 => Slave_nstate_FFd3_In15_O,
      ADR3 => Slave_nstate_FFd3_In38_0,
      O => Slave_nstate_FFd3_In41_5249
    );
  Slave_nstate_FFd4_In791 : X_LUT4
    generic map(
      INIT => X"0F0B",
      LOC => "SLICE_X16Y38"
    )
    port map (
      ADR0 => Slave_nstate_FFd4_In40_0,
      ADR1 => Slave_nstate_FFd4_In54_SW0_O,
      ADR2 => Slave_ridvalid_mux00008_0,
      ADR3 => Slave_nstate_FFd4_In28_0,
      O => Slave_nstate_FFd4_In79
    );
  Slave_nstate_FFd4 : X_SFF
    generic map(
      LOC => "SLICE_X16Y38",
      INIT => '1'
    )
    port map (
      I => Slave_nstate_FFd4_DXMUX_5280,
      CE => VCC,
      CLK => Slave_nstate_FFd4_CLKINV_5264,
      SET => GND,
      RST => GND,
      SSET => Slave_nstate_FFd4_SRINV_5265,
      SRST => GND,
      O => Slave_nstate_FFd4_1597
    );
  Slave_nstate_cmp_eq0000 : X_LUT4
    generic map(
      INIT => X"0008",
      LOC => "SLICE_X18Y38"
    )
    port map (
      ADR0 => Slave_i2cAddr(4),
      ADR1 => Slave_i2cAddr(5),
      ADR2 => Slave_i2cAddr(6),
      ADR3 => Slave_nstate_cmp_eq0000_SW0_O,
      O => Slave_nstate_cmp_eq0000_5306
    );
  Slave_delay_count_mux0000_0_111 : X_LUT4
    generic map(
      INIT => X"FFF2",
      LOC => "SLICE_X18Y22"
    )
    port map (
      ADR0 => Slave_delay_count(10),
      ADR1 => Slave_delay_count(9),
      ADR2 => N46,
      ADR3 => Slave_shiftReg_cmp_eq00001_SW1_O,
      O => Slave_delay_count_mux0000_0_111_5330
    );
  Slave_pstate_FFd1_In1311 : X_LUT4
    generic map(
      INIT => X"FFFD",
      LOC => "SLICE_X15Y34"
    )
    port map (
      ADR0 => Slave_counter(5),
      ADR1 => Slave_counter(4),
      ADR2 => Slave_pstate_FFd1_In1311_SW0_O,
      ADR3 => Slave_counter(3),
      O => Slave_nstate_FFd4_In29
    );
  Slave_Dir_mux00001601 : X_LUT4
    generic map(
      INIT => X"EA00",
      LOC => "SLICE_X20Y27"
    )
    port map (
      ADR0 => N88_0,
      ADR1 => Slave_nstate_FFd2_1691,
      ADR2 => Slave_Dir_mux000090_O,
      ADR3 => Slave_Dir_1812,
      O => Slave_Dir_mux0000160
    );
  Slave_Dir : X_SFF
    generic map(
      LOC => "SLICE_X20Y27",
      INIT => '1'
    )
    port map (
      I => Slave_Dir_DXMUX_5385,
      CE => VCC,
      CLK => Slave_Dir_CLKINV_5369,
      SET => GND,
      RST => GND,
      SSET => Slave_Dir_SRINV_5370,
      SRST => GND,
      O => Slave_Dir_1812
    );
  Slave_counter_mux0000_5_13 : X_LUT4
    generic map(
      INIT => X"40FF",
      LOC => "SLICE_X16Y32"
    )
    port map (
      ADR0 => Slave_counter(3),
      ADR1 => Slave_nstate_FFd1_1598,
      ADR2 => Slave_counter_and0000,
      ADR3 => Slave_counter_mux0000_5_13_SW0_O,
      O => Slave_counter_mux0000_5_13_5411
    );
  Slave_counter_mux0000_4_37 : X_LUT4
    generic map(
      INIT => X"F020",
      LOC => "SLICE_X14Y34"
    )
    port map (
      ADR0 => Slave_N39,
      ADR1 => Slave_counter(1),
      ADR2 => Slave_counter(0),
      ADR3 => Slave_counter_mux0000_4_23_O,
      O => Slave_counter_mux0000_4_37_5435
    );
  Slave_in_i2c_mux0000701 : X_LUT4
    generic map(
      INIT => X"AAA8",
      LOC => "SLICE_X21Y34"
    )
    port map (
      ADR0 => Slave_in_i2c_1820,
      ADR1 => Slave_in_i2c_mux00002_0,
      ADR2 => Slave_in_i2c_mux000034_O,
      ADR3 => Slave_N291,
      O => Slave_in_i2c_mux000070
    );
  Slave_in_i2c : X_SFF
    generic map(
      LOC => "SLICE_X21Y34",
      INIT => '1'
    )
    port map (
      I => Slave_in_i2c_DXMUX_5466,
      CE => VCC,
      CLK => Slave_in_i2c_CLKINV_5450,
      SET => GND,
      RST => GND,
      SSET => Slave_in_i2c_SRINV_5451,
      SRST => GND,
      O => Slave_in_i2c_1820
    );
  Slave_shiftReg_cmp_eq00001 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X18Y23"
    )
    port map (
      ADR0 => Slave_delay_count(13),
      ADR1 => Slave_delay_count(6),
      ADR2 => N46,
      ADR3 => Slave_delay_count(1),
      O => Slave_N36
    );
  Slave_ridvalid_mux00000 : X_LUT4
    generic map(
      INIT => X"C000",
      LOC => "SLICE_X17Y33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_pstate_cmp_eq0008_0,
      ADR2 => Slave_nstate_FFd1_1598,
      ADR3 => Slave_pstate_cmp_eq0009,
      O => Slave_ridvalid_mux00000_5516
    );
  Slave_pstate_FFd2_In219_SW1 : X_LUT4
    generic map(
      INIT => X"AA2A",
      LOC => "SLICE_X15Y41"
    )
    port map (
      ADR0 => Slave_pstate_FFd2_1641,
      ADR1 => Slave_DataRisingEdge_1595,
      ADR2 => OEM_I2C_Clk_IBUF_1604,
      ADR3 => Slave_pstate_FFd2_In121_1647,
      O => N99
    );
  Slave_pstate_FFd1_In15 : X_LUT4
    generic map(
      INIT => X"FFF2",
      LOC => "SLICE_X14Y39"
    )
    port map (
      ADR0 => Slave_nstate_FFd2_1691,
      ADR1 => Slave_Mcompar_pstate_cmp_gt0000_cy_5_Q,
      ADR2 => Slave_pstate_FFd1_In15_SW0_O,
      ADR3 => Slave_N311,
      O => Slave_pstate_FFd1_In15_5564
    );
  Slave_nstate_FFd3_In551 : X_LUT4
    generic map(
      INIT => X"20A0",
      LOC => "SLICE_X15Y38"
    )
    port map (
      ADR0 => Slave_nstate_FFd3_1642,
      ADR1 => Slave_DataRisingEdge_1595,
      ADR2 => Slave_nstate_FFd3_In24_O,
      ADR3 => OEM_I2C_Clk_IBUF_1604,
      O => Slave_nstate_FFd3_In55
    );
  Slave_nstate_FFd3 : X_SFF
    generic map(
      LOC => "SLICE_X15Y38",
      INIT => '0'
    )
    port map (
      I => Slave_nstate_FFd3_DXMUX_5595,
      CE => VCC,
      CLK => Slave_nstate_FFd3_CLKINV_5579,
      SET => GND,
      RST => GND,
      SSET => Slave_nstate_FFd3_SRINV_5580,
      SRST => GND,
      O => Slave_nstate_FFd3_1642
    );
  Slave_nstate_FFd3_In15_SW0 : X_LUT4
    generic map(
      INIT => X"F000",
      LOC => "SLICE_X16Y34"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Slave_counter(0),
      ADR3 => Slave_counter_and0000,
      O => N105
    );
  Slave_delay_count_mux0000_0_SW0 : X_LUT4
    generic map(
      INIT => X"FCA0",
      LOC => "SLICE_X20Y24"
    )
    port map (
      ADR0 => Slave_delay_count_or0000_1625,
      ADR1 => Slave_ClkFallingEdge_1671,
      ADR2 => Slave_delay_count(0),
      ADR3 => Slave_delay_count_mux0000_0_31_O,
      O => N50
    );
  Slave_ack_count_mux0000_0_Q : X_LUT4
    generic map(
      INIT => X"FCAC",
      LOC => "SLICE_X22Y30"
    )
    port map (
      ADR0 => Slave_N28_0,
      ADR1 => N14_0,
      ADR2 => Slave_ack_count(0),
      ADR3 => Slave_ack_count_mux0000_0_SW1_O,
      O => Slave_ack_count_mux0000(0)
    );
  Slave_ack_count_0 : X_FF
    generic map(
      LOC => "SLICE_X22Y30",
      INIT => '0'
    )
    port map (
      I => Slave_ack_count_0_DXMUX_5674,
      CE => VCC,
      CLK => Slave_ack_count_0_CLKINV_5659,
      SET => GND,
      RST => GND,
      O => Slave_ack_count(0)
    );
  Slave_pstate_FFd2_In192 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X14Y32"
    )
    port map (
      ADR0 => Slave_nstate_FFd3_1642,
      ADR1 => Slave_nstate_FFd7_1710,
      ADR2 => Slave_Mcompar_pstate_cmp_gt0000_cy_3_1,
      ADR3 => Slave_pstate_FFd2_In159_O,
      O => Slave_pstate_FFd2_In192_5699
    );
  Slave_shiftReg_mux0001_6_1 : X_LUT4
    generic map(
      INIT => X"AAA8",
      LOC => "SLICE_X20Y38"
    )
    port map (
      ADR0 => Slave_shiftReg(6),
      ADR1 => Slave_N18_0,
      ADR2 => Slave_nstate_FFd4_1597,
      ADR3 => N145,
      O => Slave_shiftReg_mux0001_6_1_5727
    );
  Slave_shiftReg_6 : X_SFF
    generic map(
      LOC => "SLICE_X20Y38",
      INIT => '0'
    )
    port map (
      I => Slave_shiftReg_6_DXMUX_5730,
      CE => VCC,
      CLK => Slave_shiftReg_6_CLKINV_5714,
      SET => GND,
      RST => GND,
      SSET => Slave_shiftReg_6_SRINV_5715,
      SRST => GND,
      O => Slave_shiftReg(6)
    );
  Slave_counter_mux0000_0_Q : X_LUT4
    generic map(
      INIT => X"EEE2",
      LOC => "SLICE_X15Y28"
    )
    port map (
      ADR0 => N135_0,
      ADR1 => Slave_counter(5),
      ADR2 => Slave_counter_mux0000_0_SW3_O,
      ADR3 => Slave_N18_0,
      O => Slave_counter_mux0000_0_Q_5758
    );
  Slave_counter_5 : X_FF
    generic map(
      LOC => "SLICE_X15Y28",
      INIT => '0'
    )
    port map (
      I => Slave_counter_5_DXMUX_5761,
      CE => VCC,
      CLK => Slave_counter_5_CLKINV_5746,
      SET => GND,
      RST => GND,
      O => Slave_counter(5)
    );
  Slave_Dir_and00001 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X22Y34"
    )
    port map (
      ADR0 => Slave_ack_count(9),
      ADR1 => Slave_ack_count(7),
      ADR2 => N96_0,
      ADR3 => N48,
      O => Slave_Dir_and0000
    );
  Slave_shiftReg_mux0001_7_1 : X_LUT4
    generic map(
      INIT => X"F0B8",
      LOC => "SLICE_X21Y39"
    )
    port map (
      ADR0 => N112_0,
      ADR1 => Slave_nstate_FFd2_1691,
      ADR2 => N111,
      ADR3 => Slave_shiftReg_mux0001_7_1_SW0_O,
      O => Slave_shiftReg_mux0001(7)
    );
  Slave_shiftReg_7 : X_FF
    generic map(
      LOC => "SLICE_X21Y39",
      INIT => '0'
    )
    port map (
      I => Slave_shiftReg_7_DXMUX_5815,
      CE => VCC,
      CLK => Slave_shiftReg_7_CLKINV_5800,
      SET => GND,
      RST => GND,
      O => Slave_shiftReg(7)
    );
  Slave_counter_mux0000_2_Q : X_LUT4
    generic map(
      INIT => X"FAD8",
      LOC => "SLICE_X15Y33"
    )
    port map (
      ADR0 => Slave_counter(3),
      ADR1 => N26_0,
      ADR2 => N25_0,
      ADR3 => Slave_N241,
      O => Slave_counter_mux0000_2_Q_5842
    );
  Slave_counter_3 : X_FF
    generic map(
      LOC => "SLICE_X15Y33",
      INIT => '0'
    )
    port map (
      I => Slave_counter_3_DXMUX_5845,
      CE => VCC,
      CLK => Slave_counter_3_CLKINV_5828,
      SET => GND,
      RST => GND,
      O => Slave_counter(3)
    );
  Slave_ridvalid_mux0000371 : X_LUT4
    generic map(
      INIT => X"CC80",
      LOC => "SLICE_X16Y28"
    )
    port map (
      ADR0 => Slave_nstate_FFd4_1597,
      ADR1 => Slave_ridvalid_1815,
      ADR2 => Slave_N211_0,
      ADR3 => Slave_ridvalid_mux000014_O,
      O => Slave_ridvalid_mux000037
    );
  Slave_ridvalid : X_SFF
    generic map(
      LOC => "SLICE_X16Y28",
      INIT => '0'
    )
    port map (
      I => Slave_ridvalid_DXMUX_5877,
      CE => VCC,
      CLK => Slave_ridvalid_CLKINV_5861,
      SET => GND,
      RST => GND,
      SSET => Slave_ridvalid_SRINV_5862,
      SRST => GND,
      O => Slave_ridvalid_1815
    );
  Slave_nstate_FFd4_In19 : X_LUT4
    generic map(
      INIT => X"FCFE",
      LOC => "SLICE_X17Y38"
    )
    port map (
      ADR0 => Slave_nstate_FFd5_1646,
      ADR1 => Slave_nstate_FFd4_In6_0,
      ADR2 => Slave_N311,
      ADR3 => Slave_nstate_cmp_eq0000_0,
      O => Slave_nstate_FFd4_In19_5903
    );
  Slave_ClkRisingEdge : X_SFF
    generic map(
      LOC => "SLICE_X18Y36",
      INIT => '0'
    )
    port map (
      I => Slave_ClkRisingEdge_DYMUX_5922,
      CE => VCC,
      CLK => Slave_ClkRisingEdge_CLKINV_5911,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => Slave_ClkRisingEdge_SRINV_5912,
      O => Slave_ClkRisingEdge_1699
    );
  Slave_delay_count_10 : X_FF
    generic map(
      LOC => "SLICE_X20Y22",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_11_DYMUX_5946,
      CE => VCC,
      CLK => Slave_delay_count_11_CLKINV_5938,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(10)
    );
  Slave_delay_count_mux0000_11_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X20Y22"
    )
    port map (
      ADR0 => Slave_delay_count_or0000_1625,
      ADR1 => Slave_delay_count_share0000(11),
      ADR2 => Slave_N3,
      ADR3 => Slave_delay_count(11),
      O => Slave_delay_count_mux0000(11)
    );
  Slave_delay_count_11 : X_FF
    generic map(
      LOC => "SLICE_X20Y22",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_11_DXMUX_5957,
      CE => VCC,
      CLK => Slave_delay_count_11_CLKINV_5938,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(11)
    );
  Slave_delay_count_12 : X_FF
    generic map(
      LOC => "SLICE_X20Y23",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_13_DYMUX_5980,
      CE => VCC,
      CLK => Slave_delay_count_13_CLKINV_5972,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(12)
    );
  Slave_delay_count_mux0000_13_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X20Y23"
    )
    port map (
      ADR0 => Slave_delay_count_share0000(13),
      ADR1 => Slave_N17_0,
      ADR2 => Slave_N3,
      ADR3 => Slave_delay_count(13),
      O => Slave_delay_count_mux0000(13)
    );
  Slave_delay_count_13 : X_FF
    generic map(
      LOC => "SLICE_X20Y23",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_13_DXMUX_5991,
      CE => VCC,
      CLK => Slave_delay_count_13_CLKINV_5972,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(13)
    );
  Slave_delay_count_14 : X_FF
    generic map(
      LOC => "SLICE_X20Y25",
      INIT => '0'
    )
    port map (
      I => Slave_delay_count_15_DYMUX_6014,
      CE => VCC,
      CLK => Slave_delay_count_15_CLKINV_6006,
      SET => GND,
      RST => GND,
      O => Slave_delay_count(14)
    );
  GLOBAL_LOGIC1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  GLOBAL_LOGIC0_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  Slave_delay_count_share0000_0_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X21Y17"
    )
    port map (
      ADR0 => Slave_delay_count(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_delay_count_share0000_0_G
    );
  Slave_delay_count_share0000_2_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X21Y18"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_delay_count(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_delay_count_share0000_2_F
    );
  Slave_delay_count_share0000_2_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X21Y18"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Slave_delay_count(3),
      ADR3 => VCC,
      O => Slave_delay_count_share0000_2_G
    );
  Slave_ack_count_addsub0000_0_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X25Y30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Slave_ack_count(1),
      ADR3 => VCC,
      O => Slave_ack_count_addsub0000_0_G
    );
  Slave_ack_count_addsub0000_2_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X25Y31"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Slave_ack_count(2),
      O => Slave_ack_count_addsub0000_2_F
    );
  Slave_ack_count_addsub0000_2_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X25Y31"
    )
    port map (
      ADR0 => Slave_ack_count(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_ack_count_addsub0000_2_G
    );
  Slave_ack_count_addsub0000_4_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X25Y32"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Slave_ack_count(4),
      ADR3 => VCC,
      O => Slave_ack_count_addsub0000_4_F
    );
  Slave_ack_count_addsub0000_4_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X25Y32"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_ack_count(5),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_ack_count_addsub0000_4_G
    );
  Slave_ack_count_addsub0000_6_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X25Y33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Slave_ack_count(6),
      O => Slave_ack_count_addsub0000_6_F
    );
  Slave_ack_count_addsub0000_6_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X25Y33"
    )
    port map (
      ADR0 => Slave_ack_count(7),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_ack_count_addsub0000_6_G
    );
  Slave_ack_count_addsub0000_8_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X25Y34"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Slave_ack_count(8),
      O => Slave_ack_count_addsub0000_8_F
    );
  Slave_ack_count_addsub0000_8_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X25Y34"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Slave_ack_count(9),
      O => Slave_ack_count_addsub0000_8_G
    );
  Slave_ack_count_addsub0000_10_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X25Y35"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_ack_count(10),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_ack_count_addsub0000_10_F
    );
  Slave_delay_count_share0000_4_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X21Y19"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Slave_delay_count(4),
      O => Slave_delay_count_share0000_4_F
    );
  Slave_delay_count_share0000_4_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X21Y19"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_delay_count(5),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_delay_count_share0000_4_G
    );
  Slave_delay_count_share0000_6_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X21Y20"
    )
    port map (
      ADR0 => Slave_delay_count(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_delay_count_share0000_6_F
    );
  Slave_delay_count_share0000_6_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X21Y20"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Slave_delay_count(7),
      O => Slave_delay_count_share0000_6_G
    );
  Slave_delay_count_share0000_8_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X21Y21"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Slave_delay_count(8),
      O => Slave_delay_count_share0000_8_F
    );
  Slave_delay_count_share0000_8_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X21Y21"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_delay_count(9),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_delay_count_share0000_8_G
    );
  Slave_delay_count_share0000_10_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X21Y22"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Slave_delay_count(10),
      O => Slave_delay_count_share0000_10_F
    );
  Slave_delay_count_share0000_10_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X21Y22"
    )
    port map (
      ADR0 => Slave_delay_count(11),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_delay_count_share0000_10_G
    );
  Slave_delay_count_share0000_12_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X21Y23"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Slave_delay_count(12),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_delay_count_share0000_12_F
    );
  Slave_delay_count_share0000_12_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X21Y23"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Slave_delay_count(13),
      ADR3 => VCC,
      O => Slave_delay_count_share0000_12_G
    );
  Slave_delay_count_share0000_14_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X21Y24"
    )
    port map (
      ADR0 => Slave_delay_count(14),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Slave_delay_count_share0000_14_F
    );
  LED_2_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD120",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_ridvalid_1815,
      O => LED_2_O
    );
  LED_3_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD119",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_doutvalid_1817,
      O => LED_3_O
    );
  OEM_ROW_EN_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_ROW_EN_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_ROW_EN_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD1",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => OEM_ROW_EN_O
    );
  OEM_VSYNC_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_VSYNC_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_VSYNC_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD172",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => OEM_VSYNC_O
    );
  OEM_PIXEL_Clk_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_PIXEL_Clk_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_PIXEL_Clk_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD2",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => OEM_PIXEL_Clk_O
    );
  IMG1_I2C_Clk_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  IMG1_I2C_Clk_OUTPUT_T1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  IMG1_I2C_Clk_OUTPUT_TFF_T1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  IMG1_I2C_Clk_OUTPUT_TFF_TMUX : X_BUF
    generic map(
      LOC => "PAD113",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => IMG1_I2C_Clk_T
    );
  IMG1_I2C_Clk_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  IMG1_I2C_Clk_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD113",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => IMG1_I2C_Clk_O
    );
  OEM_I2C_Data_OUTPUT_TFF_TMUX : X_BUF
    generic map(
      LOC => "PAD7",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Dir_1812,
      O => OEM_I2C_Data_T
    );
  OEM_I2C_Data_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD7",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_in_i2c_1820,
      O => OEM_I2C_Data_O
    );
  IMG0_RST_OUTPUT_O1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  IMG0_RST_OUTPUT_OFF_O1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  IMG0_RST_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD25",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => IMG0_RST_O
    );
  IMG0_I2C_Data_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  IMG0_I2C_Data_OUTPUT_T1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  IMG0_I2C_Data_OUTPUT_TFF_T1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  IMG0_I2C_Data_OUTPUT_TFF_TMUX : X_BUF
    generic map(
      LOC => "PAD19",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => IMG0_I2C_Data_T
    );
  IMG0_I2C_Data_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  IMG0_I2C_Data_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD19",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => IMG0_I2C_Data_O
    );
  OEM_Data_0_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_0_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_0_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD159",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => OEM_Data_0_O
    );
  OEM_Data_1_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_1_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_1_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD160",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => OEM_Data_1_O
    );
  OEM_Data_2_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_2_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_2_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD161",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => OEM_Data_2_O
    );
  OEM_Data_3_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_3_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_3_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD163",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => OEM_Data_3_O
    );
  OEM_Data_4_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_4_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_4_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD164",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => OEM_Data_4_O
    );
  OEM_Data_5_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_5_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_5_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD165",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => OEM_Data_5_O
    );
  OEM_Data_6_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_6_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_6_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD166",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => OEM_Data_6_O
    );
  OEM_Data_7_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_7_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_7_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD169",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => OEM_Data_7_O
    );
  OEM_Data_8_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_8_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_8_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD170",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => OEM_Data_8_O
    );
  OEM_Data_9_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_9_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  OEM_Data_9_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD171",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => OEM_Data_9_O
    );
  LED_0_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD122",
      PATHPULSE => 798 ps
    )
    port map (
      I => Slave_Dir_1812,
      O => LED_0_O
    );
  LED_1_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  LED_1_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  LED_1_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD121",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => LED_1_O
    );
  IMG1_RST_OUTPUT_O1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  IMG1_RST_OUTPUT_OFF_O1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  IMG1_RST_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD111",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => IMG1_RST_O
    );
  IMG1_I2C_Data_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  IMG1_I2C_Data_OUTPUT_T1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  IMG1_I2C_Data_OUTPUT_TFF_T1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  IMG1_I2C_Data_OUTPUT_TFF_TMUX : X_BUF
    generic map(
      LOC => "PAD112",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => IMG1_I2C_Data_T
    );
  IMG1_I2C_Data_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  IMG1_I2C_Data_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD112",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => IMG1_I2C_Data_O
    );
  IMG0_I2C_Clk_OUTPUT_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  IMG0_I2C_Clk_OUTPUT_T1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  IMG0_I2C_Clk_OUTPUT_TFF_T1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  IMG0_I2C_Clk_OUTPUT_TFF_TMUX : X_BUF
    generic map(
      LOC => "PAD18",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => IMG0_I2C_Clk_T
    );
  IMG0_I2C_Clk_OUTPUT_OFF_O1_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  IMG0_I2C_Clk_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD18",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => IMG0_I2C_Clk_O
    );
  NlwBlock_slave_interface_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_slave_interface_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

